tacit/minix
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arm:make the MMU fetch pagetable data through the caches.

Browse Source 
Change-Id: Ibd7b66558c369d0c0792c02801562580d255fa1f
This commit is contained in:
Kees Jongenburger 2013-09-25 11:12:46 +02:00
parent 42408472c9
commit 2f999e5753
3 changed files with 13 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
include/arch/earm/include/vm.h
View File

@ -163,6 +163,11 @@ arm/vm.h
#define ARM_VM_PFE_FS4 (1<<10) /* Fault status (bit 4) */
#define ARM_VM_PFE_FS3_0 0xf /* Fault status (bits 3:0) */
/* Translation table base register specfic flags */
#define TTBR_ADDR_MASK (0xffffc000)
#define TTBR_FLAGS_CACHED (0x1 << 3)| (0x1)
/* Fault status */
#define ARM_VM_PFE_FS(s) \
((((s) & ARM_VM_PFE_FS4) >> 6) | ((s) & ARM_VM_PFE_FS3_0))

10
kernel/arch/earm/include/cpufunc.h
View File

@ -215,16 +215,20 @@ static inline u32_t read_ttbr0()
asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
: [bar] "=r" (bar));
return bar;
return bar & TTBR_ADDR_MASK;
}
/* Write Translation Table Base Register 0 */
static inline void write_ttbr0(u32_t bar)
{
barrier();
/* In our setup TTBR contains the base address *and* the flags
but other pieces of the kernel code expect ttbr to be the
base address of the l1 page table. We therefore add the
flags here and remove them in the read_ttbr0 */
u32_t v = (bar & TTBR_ADDR_MASK ) | TTBR_FLAGS_CACHED;
asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
: : [bar] "r" (bar));
: : [bar] "r" (v));
refresh_tlb();
}

2
kernel/arch/earm/memory.c
View File

@ -303,7 +303,7 @@ int vm_lookup(const struct proc *proc, const vir_bytes virtual,
assert(HASPT(proc));
/* Retrieve page directory entry. */
root = (u32_t *) proc->p_seg.p_ttbr;
root = (u32_t *) (proc->p_seg.p_ttbr & TTBR_ADDR_MASK);
assert(!((u32_t) root % ARM_PAGEDIR_SIZE));
pde = ARM_VM_PDE(virtual);
assert(pde >= 0 && pde < ARM_VM_DIR_ENTRIES);