50e2064049
This commit removes all traces of Minix segments (the text/data/stack
memory map abstraction in the kernel) and significance of Intel segments
(hardware segments like CS, DS that add offsets to all addressing before
page table translation). This ultimately simplifies the memory layout
and addressing and makes the same layout possible on non-Intel
architectures.
There are only two types of addresses in the world now: virtual
and physical; even the kernel and processes have the same virtual
address space. Kernel and user processes can be distinguished at a
glance as processes won't use 0xF0000000 and above.
No static pre-allocated memory sizes exist any more.
Changes to booting:
. The pre_init.c leaves the kernel and modules exactly as
they were left by the bootloader in physical memory
. The kernel starts running using physical addressing,
loaded at a fixed location given in its linker script by the
bootloader. All code and data in this phase are linked to
this fixed low location.
. It makes a bootstrap pagetable to map itself to a
fixed high location (also in linker script) and jumps to
the high address. All code and data then use this high addressing.
. All code/data symbols linked at the low addresses is prefixed by
an objcopy step with __k_unpaged_*, so that that code cannot
reference highly-linked symbols (which aren't valid yet) or vice
versa (symbols that aren't valid any more).
. The two addressing modes are separated in the linker script by
collecting the unpaged_*.o objects and linking them with low
addresses, and linking the rest high. Some objects are linked
twice, once low and once high.
. The bootstrap phase passes a lot of information (e.g. free memory
list, physical location of the modules, etc.) using the kinfo
struct.
. After this bootstrap the low-linked part is freed.
. The kernel maps in VM into the bootstrap page table so that VM can
begin executing. Its first job is to make page tables for all other
boot processes. So VM runs before RS, and RS gets a fully dynamic,
VM-managed address space. VM gets its privilege info from RS as usual
but that happens after RS starts running.
. Both the kernel loading VM and VM organizing boot processes happen
using the libexec logic. This removes the last reason for VM to
still know much about exec() and vm/exec.c is gone.
Further Implementation:
. All segments are based at 0 and have a 4 GB limit.
. The kernel is mapped in at the top of the virtual address
space so as not to constrain the user processes.
. Processes do not use segments from the LDT at all; there are
no segments in the LDT any more, so no LLDT is needed.
. The Minix segments T/D/S are gone and so none of the
user-space or in-kernel copy functions use them. The copy
functions use a process endpoint of NONE to realize it's
a physical address, virtual otherwise.
. The umap call only makes sense to translate a virtual address
to a physical address now.
. Segments-related calls like newmap and alloc_segments are gone.
. All segments-related translation in VM is gone (vir2map etc).
. Initialization in VM is simpler as no moving around is necessary.
. VM and all other boot processes can be linked wherever they wish
and will be mapped in at the right location by the kernel and VM
respectively.
Other changes:
. The multiboot code is less special: it does not use mb_print
for its diagnostics any more but uses printf() as normal, saving
the output into the diagnostics buffer, only printing to the
screen using the direct print functions if a panic() occurs.
. The multiboot code uses the flexible 'free memory map list'
style to receive the list of free memory if available.
. The kernel determines the memory layout of the processes to
a degree: it tells VM where the kernel starts and ends and
where the kernel wants the top of the process to be. VM then
uses this entire range, i.e. the stack is right at the top,
and mmap()ped bits of memory are placed below that downwards,
and the break grows upwards.
Other Consequences:
. Every process gets its own page table as address spaces
can't be separated any more by segments.
. As all segments are 0-based, there is no distinction between
virtual and linear addresses, nor between userspace and
kernel addresses.
. Less work is done when context switching, leading to a net
performance increase. (8% faster on my machine for 'make servers'.)
. The layout and configuration of the GDT makes sysenter and syscall
possible.
152 lines
5.9 KiB
C
152 lines
5.9 KiB
C
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#ifndef _I386_ACONST_H
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#define _I386_ACONST_H 1
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#include <machine/interrupt.h>
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#include <machine/memory.h>
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/* Constants for protected mode. */
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/* Table sizes. */
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#define IDT_SIZE 256 /* the table is set to it's maximal size */
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/* GDT layout (SYSENTER/SYSEXIT compliant) */
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#define KERN_CS_INDEX 1
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#define KERN_DS_INDEX 2
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#define USER_CS_INDEX 3
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#define USER_DS_INDEX 4
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#define LDT_INDEX 5
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#define TSS_INDEX_FIRST 6
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#define TSS_INDEX(cpu) (TSS_INDEX_FIRST + (cpu)) /* per cpu kernel tss */
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#define GDT_SIZE (TSS_INDEX(CONFIG_MAX_CPUS)) /* LDT descriptor */
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#define SEG_SELECTOR(i) ((i)*8)
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#define KERN_CS_SELECTOR SEG_SELECTOR(KERN_CS_INDEX)
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#define KERN_DS_SELECTOR SEG_SELECTOR(KERN_DS_INDEX)
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#define USER_CS_SELECTOR (SEG_SELECTOR(USER_CS_INDEX) | USER_PRIVILEGE)
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#define USER_DS_SELECTOR (SEG_SELECTOR(USER_DS_INDEX) | USER_PRIVILEGE)
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#define LDT_SELECTOR SEG_SELECTOR(LDT_INDEX)
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#define TSS_SELECTOR(cpu) SEG_SELECTOR(TSS_INDEX(cpu))
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/* Privileges. */
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#define INTR_PRIVILEGE 0 /* kernel and interrupt handlers */
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#define USER_PRIVILEGE 3 /* servers and user processes */
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#define RPL_MASK 0x03 /* bits in selector RPL */
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/* 286 hardware constants. */
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/* Exception vector numbers. */
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#define BOUNDS_VECTOR 5 /* bounds check failed */
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#define INVAL_OP_VECTOR 6 /* invalid opcode */
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#define COPROC_NOT_VECTOR 7 /* coprocessor not available */
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#define DOUBLE_FAULT_VECTOR 8
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#define COPROC_SEG_VECTOR 9 /* coprocessor segment overrun */
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#define INVAL_TSS_VECTOR 10 /* invalid TSS */
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#define SEG_NOT_VECTOR 11 /* segment not present */
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#define STACK_FAULT_VECTOR 12 /* stack exception */
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#define PROTECTION_VECTOR 13 /* general protection */
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/* Selector bits. */
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#define TI 0x04 /* table indicator */
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#define RPL 0x03 /* requester privilege level */
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/* Base and limit sizes and shifts. */
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#define BASE_MIDDLE_SHIFT 16 /* shift for base --> base_middle */
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/* Access-byte and type-byte bits. */
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#define PRESENT 0x80 /* set for descriptor present */
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#define DPL 0x60 /* descriptor privilege level mask */
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#define DPL_SHIFT 5
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#define SEGMENT 0x10 /* set for segment-type descriptors */
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/* Access-byte bits. */
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#define EXECUTABLE 0x08 /* set for executable segment */
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#define CONFORMING 0x04 /* set for conforming segment if executable */
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#define EXPAND_DOWN 0x04 /* set for expand-down segment if !executable*/
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#define READABLE 0x02 /* set for readable segment if executable */
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#define WRITEABLE 0x02 /* set for writeable segment if !executable */
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#define TSS_BUSY 0x02 /* set if TSS descriptor is busy */
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#define ACCESSED 0x01 /* set if segment accessed */
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/* Special descriptor types. */
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#define AVL_286_TSS 1 /* available 286 TSS */
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#define LDT 2 /* local descriptor table */
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#define BUSY_286_TSS 3 /* set transparently to the software */
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#define CALL_286_GATE 4 /* not used */
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#define TASK_GATE 5 /* only used by debugger */
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#define INT_286_GATE 6 /* interrupt gate, used for all vectors */
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#define TRAP_286_GATE 7 /* not used */
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#define INT_GATE_TYPE (INT_286_GATE | DESC_386_BIT)
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#define TSS_TYPE (AVL_286_TSS | DESC_386_BIT)
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/* Extra 386 hardware constants. */
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/* Exception vector numbers. */
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#define PAGE_FAULT_VECTOR 14
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#define COPROC_ERR_VECTOR 16 /* coprocessor error */
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#define ALIGNMENT_CHECK_VECTOR 17
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#define MACHINE_CHECK_VECTOR 18
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#define SIMD_EXCEPTION_VECTOR 19 /* SIMD Floating-Point Exception (#XM) */
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/* Descriptor structure offsets. */
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#define DESC_GRANULARITY 6 /* to granularity byte */
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#define DESC_BASE_HIGH 7 /* to base_high */
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/* Type-byte bits. */
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#define DESC_386_BIT 0x08 /* 386 types are obtained by ORing with this */
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/* LDT's and TASK_GATE's don't need it */
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/* Base and limit sizes and shifts. */
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#define BASE_HIGH_SHIFT 24 /* shift for base --> base_high */
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#define BYTE_GRAN_MAX 0xFFFFFL /* maximum size for byte granular segment */
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#define GRANULARITY_SHIFT 16 /* shift for limit --> granularity */
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#define OFFSET_HIGH_SHIFT 16 /* shift for (gate) offset --> offset_high */
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#define PAGE_GRAN_SHIFT 12 /* extra shift for page granular limits */
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/* Granularity byte. */
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#define GRANULAR 0x80 /* set for 4K granularilty */
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#define DEFAULT 0x40 /* set for 32-bit defaults (executable seg) */
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#define BIG 0x40 /* set for "BIG" (expand-down seg) */
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#define AVL 0x10 /* 0 for available */
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#define LIMIT_HIGH 0x0F /* mask for high bits of limit */
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/* Program stack words and masks. */
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#define INIT_PSW 0x0200 /* initial psw */
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#define INIT_TASK_PSW 0x1200 /* initial psw for tasks (with IOPL 1) */
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#define TRACEBIT 0x0100 /* OR this with psw in proc[] for tracing */
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#define SETPSW(rp, new) /* permits only certain bits to be set */ \
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((rp)->p_reg.psw = ((rp)->p_reg.psw & ~0xCD5) | ((new) & 0xCD5))
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#define IF_MASK 0x00000200
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#define IOPL_MASK 0x003000
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#define INTEL_CPUID_GEN_EBX 0x756e6547 /* ASCII value of "Genu" */
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#define INTEL_CPUID_GEN_EDX 0x49656e69 /* ASCII value of "ineI" */
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#define INTEL_CPUID_GEN_ECX 0x6c65746e /* ASCII value of "ntel" */
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#define AMD_CPUID_GEN_EBX 0x68747541 /* ASCII value of "Auth" */
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#define AMD_CPUID_GEN_EDX 0x69746e65 /* ASCII value of "enti" */
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#define AMD_CPUID_GEN_ECX 0x444d4163 /* ASCII value of "cAMD" */
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#define CPU_VENDOR_INTEL 0
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#define CPU_VENDOR_AMD 2
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#define CPU_VENDOR_UNKNOWN 0xff
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/* fpu context should be saved in 16-byte aligned memory */
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#define FPUALIGN 16
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/* Poweroff 16-bit code address */
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#define BIOS_POWEROFF_ENTRY 0x1000
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/*
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* defines how many bytes are reserved at the top of the kernel stack for global
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* information like currently scheduled process or current cpu id
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*/
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#define X86_STACK_TOP_RESERVED (2 * sizeof(reg_t))
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#define PG_ALLOCATEME ((phys_bytes)-1)
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#endif /* _I386_ACONST_H */
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