tacit/minix
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Changes after review

Browse Source 
Change-Id: I6ad261b5b00f34cc389789c707e8d91c45683007
This commit is contained in:
Michal Maka 2013-08-02 15:01:07 +02:00 committed by Ben Gras
parent b05d70e94c
commit f9bdbf1089
5 changed files with 633 additions and 539 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/lan8710a/README.txt
View File

@ -22,12 +22,12 @@ Restart the system and the driver should work.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Driver was tested using various tools, i. e. Driver was tested using various tools, i. e.
* fetch - downloading file from the Internet and also local server. Every file * fetch - downloading file from the Internet and also local server. Every file
downloaded well, but speed was about 50-200 kB/s. downloaded well, but speed was about 50-200 kB/s.
* ftp - downloading and uploading 20 MB file completed. * ftp - downloading and uploading 20 MB file completed.
* ping - checking connection between BeagleBone and computer passed using standard * ping - checking connection between BeagleBone and computer passed using stan -
settings, when we set ping requests interval to 200 ms it also passed. But with dard settings, when we set ping requests interval to 200 ms it also
20 ms and 2 ms driver dropped some packets (20 ms - about 20% loss, 2 ms - 50% passed. But with 20 ms and 2 ms driver dropped some packets (20 ms -
loss). about 20% loss, 2 ms - 50% loss).
* udpstat, hostaddr, dhcpd, ifconfig, arp gave proper results. * udpstat, hostaddr, dhcpd, ifconfig, arp gave proper results.
Tests passed, so driver meets the requirements of ethernet driver. Tests passed, so driver meets the requirements of ethernet driver.

1004
drivers/lan8710a/lan8710a.c
View File

File diff suppressed because it is too large Load Diff

10
drivers/lan8710a/lan8710a.conf
View File

@ -9,9 +9,9 @@ service lan8710a
DEVIO # 21 DEVIO # 21
; ;
ipc ipc
SYSTEM pm rs log tty ds vm tty inet lwip
inet lwip ; ;
irq 41; # IRQ 41 allowed irq 41 # IRQ 41 allowed
irq 42; # IRQ 42 allowed 42 # IRQ 42 allowed
uid 0; ;
}; };

46
drivers/lan8710a/lan8710a.h
View File

@ -7,11 +7,11 @@
#if LAN8710A_DEBUG == 1 #if LAN8710A_DEBUG == 1
#define LAN8710A_DEBUG_PRINT(args) \ #define LAN8710A_DEBUG_PRINT(args) \
{ \ do { \
printf("LAN8710A DEBUG: "); \ printf("LAN8710A DEBUG: "); \
printf args; \ printf args; \
printf("\n"); \ printf("\n"); \
} } while (0)
#else #else
#define LAN8710A_DEBUG_PRINT(args) #define LAN8710A_DEBUG_PRINT(args)
#endif #endif
@ -23,7 +23,10 @@
#define OK 0 /* general OK flag */ #define OK 0 /* general OK flag */
#endif #endif
#define MAP_FAILED ((void *) -1) /* mmap() failed */ #define MAP_FAILED ((void *) -1) /* mmap() failed */
/* Ethernet driver defines */
#define LAN8710A_NAME_LEN (11)
/* Ethernet driver states */ /* Ethernet driver states */
#define LAN8710A_DETECTED (1 << 0) #define LAN8710A_DETECTED (1 << 0)
@ -34,17 +37,17 @@
#define LAN8710A_TRANSMIT (1 << 5) #define LAN8710A_TRANSMIT (1 << 5)
/* Descriptors flags */ /* Descriptors flags */
#define LAN8710A_DESC_FLAG_OWN (1 << 29) /* ownership flag */ #define LAN8710A_DESC_FLAG_OWN (1 << 29) /* ownership flag */
#define LAN8710A_DESC_FLAG_SOP (1 << 31) /* start of packet flag */ #define LAN8710A_DESC_FLAG_SOP (1 << 31) /* start of packet flag */
#define LAN8710A_DESC_FLAG_EOP (1 << 30) /* end of packet flag */ #define LAN8710A_DESC_FLAG_EOP (1 << 30) /* end of packet flag */
/* Number of Tx and Rx interrupts */ /* Number of Tx and Rx interrupts */
#define LAN8710A_RX_INTR (41) #define LAN8710A_RX_INTR (41)
#define LAN8710A_TX_INTR (42) #define LAN8710A_TX_INTR (42)
/* Values to be written after interrupt handle */ /* Values to be written after interrupt handle and interrupt masks*/
#define END_OF_RX_INT (1) #define RX_INT (1)
#define END_OF_TX_INT (2) #define TX_INT (2)
/** Numbers of Tx DMA channels */ /** Numbers of Tx DMA channels */
#define TX_DMA_CHANNELS (8) #define TX_DMA_CHANNELS (8)
@ -71,34 +74,33 @@
#define TX_DESC_TO_PORT1 (1 << 16) #define TX_DESC_TO_PORT1 (1 << 16)
#define TX_DESC_TO_PORT_EN (1 << 20) #define TX_DESC_TO_PORT_EN (1 << 20)
typedef struct lan8710a_desc typedef struct lan8710a_desc_t
{ {
u32_t next_pointer; u32_t next_pointer;
u32_t buffer_pointer; u32_t buffer_pointer;
u32_t buffer_length_off; u32_t buffer_length_off;
u32_t pkt_len_flags; u32_t pkt_len_flags;
} } lan8710a_desc_t;
lan8710a_desc_t;
typedef struct lan8710a typedef struct lan8710a_t
{ {
lan8710a_desc_t *rx_desc; lan8710a_desc_t *rx_desc;
lan8710a_desc_t *tx_desc; lan8710a_desc_t *tx_desc;
phys_bytes rx_desc_phy; phys_bytes rx_desc_phy;
phys_bytes tx_desc_phy; phys_bytes tx_desc_phy;
char name[11]; char name[LAN8710A_NAME_LEN];
int status; int status;
int irq_rx_hook; /* Rx interrupt Request Vector Hook. */ int irq_rx_hook; /* Rx interrupt Request Vector Hook. */
int irq_tx_hook; /* Tx interrupt Request Vector Hook. */ int irq_tx_hook; /* Tx interrupt Request Vector Hook. */
int instance; int instance;
ether_addr_t address; /* Ethernet MAC address. */ ether_addr_t address; /* Ethernet MAC address. */
u8_t *regs; u8_t *regs;
u32_t phy_address; u32_t phy_address;
u8_t *p_rx_buf; /* pointer to the buffer with receive frames */ u8_t *p_rx_buf; /* pointer to the buffer with receive frames */
u8_t *p_tx_buf; /* pointer to the buffer with transmit frames */ u8_t *p_tx_buf; /* pointer to the buffer with transmit frames */
u16_t tx_desc_idx; /* index of the next transmit desciptor */ u16_t tx_desc_idx; /* index of the next transmit desciptor */
u16_t rx_desc_idx; /* index of the next receive desciptor */ u16_t rx_desc_idx; /* index of the next receive desciptor */
int client; int client;
message tx_message; message tx_message;
message rx_message; message rx_message;
@ -115,7 +117,7 @@ typedef struct lan8710a
vir_bytes regs_cpsw_ale; vir_bytes regs_cpsw_ale;
vir_bytes regs_cpsw_wr; vir_bytes regs_cpsw_wr;
vir_bytes regs_intc; vir_bytes regs_intc;
vir_bytes regs_cpdma_stateram; vir_bytes regs_cpdma_stram;
} lan8710a_t; } lan8710a_t;
#endif /* LAN8710A_H_ */ #endif /* LAN8710A_H_ */

98
drivers/lan8710a/lan8710a_reg.h
View File

@ -2,7 +2,7 @@
#define LAN8710A_REG_H_ #define LAN8710A_REG_H_
/* How much memory we should map */ /* How much memory we should map */
#define MEMORY_LIMIT (0x5302000) #define MEMORY_LIMIT (0x5302000)
#define BEGINNING_DESC_MEM (0x4A102000) #define BEGINNING_DESC_MEM (0x4A102000)
#define DESC_MEMORY_LIMIT (0x2000) #define DESC_MEMORY_LIMIT (0x2000)
#define BEGINNING_RX_DESC_MEM (0x4A102000) #define BEGINNING_RX_DESC_MEM (0x4A102000)
@ -10,20 +10,20 @@
/* MDIO Registers */ /* MDIO Registers */
#define MDIO_BASE_ADDR (0x4A101000) #define MDIO_BASE_ADDR (0x4A101000)
#define MDIOVER ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x00)) #define MDIOVER ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x00))
#define MDIOCONTROL ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x04)) #define MDIOCONTROL ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x04))
#define MDIOALIVE ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x08)) #define MDIOALIVE ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x08))
#define MDIOLINK ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x0C)) #define MDIOLINK ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x0C))
#define MDIOLINKINTRAW ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x10)) #define MDIOLINKINTRAW ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x10))
#define MDIOLINKINTMASKED ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x14)) #define MDIOLINKINTMASKED ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x14))
#define MDIOUSERINTRAW ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x20)) #define MDIOUSERINTRAW ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x20))
#define MDIOUSERINTMASKED ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x24)) #define MDIOUSERINTMASKED ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x24))
#define MDIOUSERINTMASKSET ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x28)) #define MDIOUSERINTMASKSET ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x28))
#define MDIOUSERINTMASKCLR ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x2C)) #define MDIOUSERINTMASKCLR ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x2C))
#define MDIOUSERACCESS0 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x80)) #define MDIOUSERACCESS0 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x80))
#define MDIOUSERPHYSEL0 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x84)) #define MDIOUSERPHYSEL0 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x84))
#define MDIOUSERACCESS1 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x88)) #define MDIOUSERACCESS1 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x88))
#define MDIOUSERPHYSEL1 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x8C)) #define MDIOUSERPHYSEL1 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x8C))
#define MDIO_PREAMBLE (1 << 20) #define MDIO_PREAMBLE (1 << 20)
#define MDCLK_DIVIDER (0x255) #define MDCLK_DIVIDER (0x255)
@ -90,8 +90,8 @@
/* CPSW_SL Registers */ /* CPSW_SL Registers */
#define CPSW_SL_BASE_ADR (0x4A100D80) #define CPSW_SL_BASE_ADR (0x4A100D80)
#define CPSW_SL_MACCONTROL(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x04)) #define CPSW_SL_MACCONTROL(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x04))
#define CPSW_SL_SOFT_RESET(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x0C)) #define CPSW_SL_SOFT_RESET(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x0C))
#define CPSW_SL_RX_MAXLEN(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x10)) #define CPSW_SL_RX_MAXLEN(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x10))
#define CPSW_SL_BOFFTEST(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x14)) #define CPSW_SL_BOFFTEST(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x14))
#define CPSW_SL_EMCONTROL(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x20)) #define CPSW_SL_EMCONTROL(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x20))
@ -104,16 +104,16 @@
/* CPSW_STATS Registers */ /* CPSW_STATS Registers */
#define CPSW_STATS_BASE_ADR (0x4A100900) #define CPSW_STATS_BASE_ADR (0x4A100900)
#define CPSW_STATS_MEM_LIMIT (0x90) #define CPSW_STATS_MEM_LIMIT (0x90)
#define CPSW_STAT_RX_GOOD ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x00)) #define CPSW_STAT_RX_GOOD ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x00))
#define CPSW_STAT_RX_CRC_ERR ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x10)) #define CPSW_STAT_RX_CRC_ERR ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x10))
#define CPSW_STAT_RX_AGNCD_ERR ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x14)) #define CPSW_STAT_RX_AGNCD_ERR ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x14))
#define CPSW_STAT_RX_OVERSIZE ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x18)) #define CPSW_STAT_RX_OVERSIZE ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x18))
#define CPSW_STAT_TX_GOOD ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x34)) #define CPSW_STAT_TX_GOOD ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x34))
#define CPSW_STAT_COLLISIONS ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x48)) #define CPSW_STAT_COLLISIONS ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x48))
#define CPSW_STAT_TX_UNDERRUN ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x5C)) #define CPSW_STAT_TX_UNDERRUN ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x5C))
#define CPSW_STAT_CARR_SENS_ERR ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x60)) #define CPSW_STAT_CARR_SENS_ERR ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x60))
#define CPSW_STAT_RX_OVERRUN ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x8C)) #define CPSW_STAT_RX_OVERRUN ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x8C))
/* CPSW_CPDMA Registers */ /* CPSW_CPDMA Registers */
#define CPSW_CPDMA_BASE_ADR (0x4A100800) #define CPSW_CPDMA_BASE_ADR (0x4A100800)
@ -122,17 +122,17 @@
#define CPDMA_RX_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x14)) #define CPDMA_RX_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x14))
#define CPDMA_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x20)) #define CPDMA_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x20))
#define CPDMA_STATUS ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x24)) #define CPDMA_STATUS ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x24))
#define CPDMA_RX_BUFFER_OFFSET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x28)) #define CPDMA_RX_BUFFER_OFFSET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x28))
#define CPDMA_EMCONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x2C)) #define CPDMA_EMCONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x2C))
#define CPDMA_TX_INTMASK_SET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x88)) #define CPDMA_TX_INTMASK_SET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x88))
#define CPDMA_TX_INTMASK_CLEAR ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x8C)) #define CPDMA_TX_INTMASK_CLEAR ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x8C))
#define CPDMA_EOI_VECTOR ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x94)) #define CPDMA_EOI_VECTOR ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x94))
#define CPDMA_RX_INTMASK_SET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0xA8)) #define CPDMA_RX_INTMASK_SET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0xA8))
#define CPDMA_RX_INTMASK_CLEAR ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0xAC)) #define CPDMA_RX_INTMASK_CLEAR ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0xAC))
#define CPDMA_IDLE (1 << 31) #define CPDMA_IDLE (1 << 31)
#define CPDMA_TX_RLIM (0xFF << 8) #define CPDMA_TX_RLIM (0xFF << 8)
#define CPDMA_NO_OFFSET (oxFFFF << 0) #define CPDMA_NO_OFFSET (0xFFFF << 0)
#define CPDMA_RX_CEF (1 << 4) #define CPDMA_RX_CEF (1 << 4)
#define CPDMA_CMD_IDLE (1 << 3) #define CPDMA_CMD_IDLE (1 << 3)
#define RX_OFFLEN_BLOCK (1 << 2) #define RX_OFFLEN_BLOCK (1 << 2)
@ -140,7 +140,7 @@
#define TX_PTYPE (1 << 0) #define TX_PTYPE (1 << 0)
#define CPDMA_TX_EN (1 << 0) #define CPDMA_TX_EN (1 << 0)
#define CPDMA_RX_EN (1 << 0) #define CPDMA_RX_EN (1 << 0)
#define CPDMA_FIRST_CHAN_INT (1 << 0) #define CPDMA_FIRST_CHAN_INT (1 << 0)
#define CPDMA_ALL_CHAN_INT (0xFF << 0) #define CPDMA_ALL_CHAN_INT (0xFF << 0)
#define CPDMA_TX_PTYPE (1 << 0) #define CPDMA_TX_PTYPE (1 << 0)
#define CPDMA_ERROR (0x00F7F700) #define CPDMA_ERROR (0x00F7F700)
@ -148,8 +148,8 @@
/* CPSW_SS Registers */ /* CPSW_SS Registers */
#define CPSW_SS_BASE_ADR (0x4A100000) #define CPSW_SS_BASE_ADR (0x4A100000)
#define CPSW_SS_SOFT_RESET ((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x08)) #define CPSW_SS_SOFT_RESET ((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x08))
#define CPSW_SS_STAT_PORT_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x0C)) #define CPSW_SS_STAT_PORT_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x0C))
#define CPSW_SS_TX_START_WDS ((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x20)) #define CPSW_SS_TX_START_WDS ((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x20))
#define CPSW_P2_STAT_EN (1 << 2) #define CPSW_P2_STAT_EN (1 << 2)
#define CPSW_P1_STAT_EN (1 << 1) #define CPSW_P1_STAT_EN (1 << 1)
@ -165,15 +165,15 @@
#define CPSW_WR_C0_TX_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x18)) #define CPSW_WR_C0_TX_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x18))
#define CPSW_WR_C0_TX_STAT ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x48)) #define CPSW_WR_C0_TX_STAT ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x48))
#define CPSW_FIRST_CHAN_INT (1 << 0) #define CPSW_FIRST_CHAN_INT (1 << 0)
#define CPSW_ALL_CHAN_INT (0xFF << 0) #define CPSW_ALL_CHAN_INT (0xFF << 0)
/* INTERRUPTION CONTROLLER Registers */ /* INTERRUPTION CONTROLLER Registers */
#define INTC_BASE_ADR (0x48200000) #define INTC_BASE_ADR (0x48200000)
#define INTC_SYSCONFIG ((volatile u32_t *)( lan8710a_state.regs_intc + 0x10)) #define INTC_SYSCONFIG ((volatile u32_t *)( lan8710a_state.regs_intc + 0x10))
#define INTC_IDLE ((volatile u32_t *)( lan8710a_state.regs_intc + 0x50)) #define INTC_IDLE ((volatile u32_t *)( lan8710a_state.regs_intc + 0x50))
#define INTC_MIR_CLEAR1 ((volatile u32_t *)( lan8710a_state.regs_intc + 0xA8)) #define INTC_MIR_CLEAR1 ((volatile u32_t *)( lan8710a_state.regs_intc + 0xA8))
#define INTC_ILR(x) ((volatile u32_t *)( lan8710a_state.regs_intc + 0x100 + 4*(x))) #define INTC_ILR(x) ((volatile u32_t *)( lan8710a_state.regs_intc + 0x100 + 4*(x)))
#define INTC_AUTOIDLE (1 << 0) #define INTC_AUTOIDLE (1 << 0)
#define INTC_FUNCIDLE (1 << 0) #define INTC_FUNCIDLE (1 << 0)
@ -183,21 +183,21 @@
#define INTC_TX_MASK (1 << 10) #define INTC_TX_MASK (1 << 10)
/* DMA STATERAM Registers */ /* DMA STATERAM Registers */
#define CPDMA_STATERAM_BASE_ADR (0x4A100A00) #define CPDMA_STRAM_BASE_ADR (0x4A100A00)
#define CPDMA_STATERAM_TX_HDP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stateram + 4*(x))) #define CPDMA_STRAM_TX_HDP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 4*(x)))
#define CPDMA_STATERAM_RX_HDP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stateram + 0x20 + 4*(x))) #define CPDMA_STRAM_RX_HDP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 0x20 + 4*(x)))
#define CPDMA_STATERAM_TX_CP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stateram + 0x40 + 4*(x))) #define CPDMA_STRAM_TX_CP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 0x40 + 4*(x)))
#define CPDMA_STATERAM_RX_CP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stateram + 0x60 + 4*(x))) #define CPDMA_STRAM_RX_CP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 0x60 + 4*(x)))
#define ALL_BITS (0xFFFFFFFF) #define ALL_BITS (0xFFFFFFFF)
/* LAN8710A Registers */ /* LAN8710A Registers */
#define PHY_REGISTERS (31) #define PHY_REGISTERS (31)
#define LAN8710A_CTRL_REG (0) #define LAN8710A_CTRL_REG (0)
#define LAN8710A_STATUS_REG (1) #define LAN8710A_STATUS_REG (1)
#define LAN8710A_SOFT_RESET (1 << 15) #define LAN8710A_SOFT_RESET (1 << 15)
#define LAN8710A_AUTO_NEG (1 << 12) #define LAN8710A_AUTO_NEG (1 << 12)
#define LAN8710A_AUTO_NEG_COMPL (1 << 5) #define LAN8710A_AUTO_NEG_COMPL (1 << 5)
#endif /* LAN8710A_REG_H_ */ #endif /* LAN8710A_REG_H_ */