diff --git a/include/minix/padconf.h b/include/minix/padconf.h
index ba09a1c99..ee5d51995 100644
--- a/include/minix/padconf.h
+++ b/include/minix/padconf.h
@@ -5,15 +5,15 @@
  * The base must be page aligned, so we round down and the kernel adds the
  * offset. The size must be a multiple of ARM_PAGE_SIZE, so we round up to 4KB.
  */
-#ifdef AM335X
-#define PADCONF_REGISTERS_BASE 0x44E10000
-#define PADCONF_REGISTERS_OFFSET 0x0000
-#define PADCONF_REGISTERS_SIZE 0x1000 /* OFFSET + highest reg, rounded up */
-#elif DM37XX
-#define PADCONF_REGISTERS_BASE 0x48002000
-#define PADCONF_REGISTERS_OFFSET 0x0030
-#define PADCONF_REGISTERS_SIZE 0x1000 /* OFFSET + highest reg, rounded up */
-#endif
+//#ifdef AM335X
+#define PADCONF_AM335X_REGISTERS_BASE 0x44E10000
+#define PADCONF_AM335X_REGISTERS_OFFSET 0x0000
+#define PADCONF_AM335X_REGISTERS_SIZE 0x1000 /* OFFSET + highest reg, rounded up */
+//#elif DM37XX
+#define PADCONF_DM37XX_REGISTERS_BASE 0x48002000
+#define PADCONF_DM37XX_REGISTERS_OFFSET 0x0030
+#define PADCONF_DM37XX_REGISTERS_SIZE 0x1000 /* OFFSET + highest reg, rounded up */
+//#endif
 
 #define PADCONF_MUXMODE(X)  (X & 0x7)	/* mode 1 til 7 [2:0] */
 #define PADCONF_PULL_MODE(X)  ((X & 0x3) << 3)	/* 2 bits[4:3] */
diff --git a/kernel/arch/earm/arch_clock.c b/kernel/arch/earm/arch_clock.c
index 754c6ccde..b045ca75c 100644
--- a/kernel/arch/earm/arch_clock.c
+++ b/kernel/arch/earm/arch_clock.c
@@ -7,6 +7,7 @@
 #include "kernel/proc.h"
 #include "kernel/interrupt.h"
 #include <minix/u64.h>
+#include <minix/board.h>
 #include "kernel/glo.h"
 #include "kernel/profile.h"
 
@@ -28,12 +29,14 @@ int init_local_timer(unsigned freq)
 {
 	omap3_timer_init(freq);
 	omap3_frclock_init();
-#ifdef DM37XX
-	tsc_per_ms[0] = 16250;
-#endif
-#ifdef AM335X
-	tsc_per_ms[0] = 15000;
-#endif
+
+	if (BOARD_IS_BBXM(machine.board_id)){
+		tsc_per_ms[0] = 16250;
+	} else if (BOARD_IS_BB(machine.board_id)){
+		tsc_per_ms[0] = 15000;
+	} else {
+		panic("Can not do the clock setup. machine (0x%08x) is unknown\n",machine.board_id);
+	};
 
 	return 0;
 }
diff --git a/kernel/arch/earm/do_padconf.c b/kernel/arch/earm/do_padconf.c
index 544fa49bd..e1087ec5f 100644
--- a/kernel/arch/earm/do_padconf.c
+++ b/kernel/arch/earm/do_padconf.c
@@ -4,9 +4,9 @@
 #if USE_PADCONF
 
 /* get arch specific arch_padconf_set() */
-#if defined(AM335X) || defined(DM37XX)
+//#if defined(AM335X) || defined(DM37XX)
 #include "omap_padconf.h"
-#endif
+//#endif
 
 /*===========================================================================*
  *                                do_padconf                                 *
diff --git a/kernel/arch/earm/include/cpufunc.h b/kernel/arch/earm/include/cpufunc.h
index c5606dbe4..318c992c5 100644
--- a/kernel/arch/earm/include/cpufunc.h
+++ b/kernel/arch/earm/include/cpufunc.h
@@ -410,6 +410,17 @@ static inline void write_vbar(u32_t vbar)
 	isb();
 }
 
+#define MIDR_IMPLEMENTER_SHIFT (24)
+#define MIDR_IMPLEMENTER_MASK (0xFF << MIDR_IMPLEMENTER_SHIFT)
+#define MIDR_MAJOR_REV_SHIFT (20)
+#define MIDR_MAJOR_REV_MASK (0xF << MIDR_MAJOR_REV_SHIFT)
+#define MIDR_ARCH_CODE_SHIFT (16)
+#define MIDR_ARCH_CODE_MASK (0xF << MIDR_ARCH_CODE_SHIFT)
+#define MIDR_PART_NUMBER_SHIFT (4)
+#define MIDR_PART_NUMBER_MASK (0xFFF << MIDR_PART_NUMBER_SHIFT)
+#define MIDR_MINOR_REV_SHIFT (0)
+#define MIDR_MINOR_REV_MASK (0xF << MIDR_MINOR_REV_SHIFT)
+
 /* Read the Main ID Register  */
 static inline u32_t read_midr()
 {
diff --git a/kernel/arch/earm/memory.c b/kernel/arch/earm/memory.c
index 4da9f118b..faa48ce51 100644
--- a/kernel/arch/earm/memory.c
+++ b/kernel/arch/earm/memory.c
@@ -6,6 +6,7 @@
 #include <machine/vm.h>
 
 #include <minix/type.h>
+#include <minix/board.h>
 #include <minix/syslib.h>
 #include <minix/cpufeature.h>
 #include <string.h>
@@ -737,12 +738,13 @@ int arch_phys_map(const int index,
 	}
 	else if (index == frclock_index) {
 
-#ifdef DM37XX
-		*addr = OMAP3_GPTIMER10_BASE;
-#endif
-#ifdef AM335X
-		*addr = AM335X_DMTIMER7_BASE;
-#endif
+		if (BOARD_IS_BBXM(machine.board_id)){
+			*addr = OMAP3_GPTIMER10_BASE;
+		} else if (BOARD_IS_BB(machine.board_id)){
+			*addr = AM335X_DMTIMER7_BASE;
+		} else {
+			panic("Can not do the clock setup. machine (0x%08x) is unknown\n",machine.board_id);
+		};
 		*len = ARM_PAGE_SIZE;
 		*flags = VMMF_UNCACHED | VMMF_USER;
 		return OK;
@@ -792,15 +794,15 @@ int arch_phys_map_reply(const int index, const vir_bytes addr)
 		return OK;
 	}
 	else if (index == frclock_index) {
-#if defined(DM37XX)
-		minix_kerninfo.minix_frclock_tcrr = addr + OMAP3_TIMER_TCRR;
-		minix_kerninfo.minix_arm_frclock_hz = 1625000;
-#elif defined(AM335X) 
-		minix_kerninfo.minix_frclock_tcrr = addr + AM335X_TIMER_TCRR;
-		minix_kerninfo.minix_arm_frclock_hz = 1500000;
-#else
-#error ARM: plese define either AM335X or DM37XX.
-#endif
+		if (BOARD_IS_BBXM(machine.board_id)){
+			minix_kerninfo.minix_frclock_tcrr = addr + OMAP3_TIMER_TCRR;
+			minix_kerninfo.minix_arm_frclock_hz = 1625000;
+		} else if (BOARD_IS_BB(machine.board_id)){
+			minix_kerninfo.minix_frclock_tcrr = addr + AM335X_TIMER_TCRR;
+			minix_kerninfo.minix_arm_frclock_hz = 1500000;
+		} else {
+			panic("memory setup errot machine (0x%08x) is unhandled\n",machine.board_id);
+		};
 
 		return OK;
 	}
diff --git a/kernel/arch/earm/omap_intr.c b/kernel/arch/earm/omap_intr.c
index a99b8c6a1..7dac821a6 100644
--- a/kernel/arch/earm/omap_intr.c
+++ b/kernel/arch/earm/omap_intr.c
@@ -1,6 +1,7 @@
 #include <sys/types.h>
 #include <machine/cpu.h>
 #include <minix/type.h>
+#include <minix/board.h>
 #include <io.h>
 
 #include "kernel/kernel.h"
@@ -21,12 +22,13 @@ static kern_phys_map intr_phys_map;
 
 int intr_init(const int auto_eoi)
 {
-#ifdef DM37XX
-    omap_intr.base = OMAP3_DM37XX_INTR_BASE;
-#endif
-#ifdef AM335X
-    omap_intr.base = OMAP3_AM335X_INTR_BASE;
-#endif
+    if (BOARD_IS_BBXM(machine.board_id)){
+	omap_intr.base = OMAP3_DM37XX_INTR_BASE;
+    } else if (BOARD_IS_BB(machine.board_id)){
+	omap_intr.base = OMAP3_AM335X_INTR_BASE;
+    } else {
+	panic("Can not do the interrupt setup. machine (0x%08x) is unknown\n",machine.board_id);
+    };
     omap_intr.size = 0x1000 ; /* 4K */
 
     kern_phys_map_ptr(omap_intr.base,omap_intr.size,
diff --git a/kernel/arch/earm/omap_intr.h b/kernel/arch/earm/omap_intr.h
index 32e7eaca7..60c53aefb 100644
--- a/kernel/arch/earm/omap_intr.h
+++ b/kernel/arch/earm/omap_intr.h
@@ -1,16 +1,16 @@
 #ifndef _OMAP_INTR_H
 #define _OMAP_INTR_H
 
-#ifdef DM37XX
+//#ifdef DM37XX
 /* Interrupt controller memory map */
 #define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
 
-#endif /* DM37XX */
+//#endif /* DM37XX */
 
-#ifdef AM335X
+//#ifdef AM335X
 /* Interrupt controller memory map */
 #define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
-#endif /* AM335X */
+//#endif /* AM335X */
 
 /* Interrupt controller registers */
 #define OMAP3_INTCPS_REVISION     0x000 /* IP revision code */
@@ -59,7 +59,7 @@
 
 
 
-#ifdef DM37XX
+//#ifdef DM37XX
 
 #define OMAP3_DM337X_NR_IRQ_VECTORS    96
 
@@ -135,9 +135,9 @@
 #define OMAP3_HSUSB_DMA_IRQ 93  /* High-speed USB OTG DMA */
 #define OMAP3_MMC3_IRQ      94  /* MMC/SD module 3 */
 
-#endif
+//#endif
 
-#ifdef AM335X
+//#ifdef AM335X
 #define AM335X_INT_EMUINT                         0	/* Emulation interrupt (EMUICINTR) */
 #define AM335X_INT_COMMTX                         1	/* CortexA8 COMMTX */
 #define AM335X_INT_COMMRX                         2	/* CortexA8 COMMRX */
@@ -239,7 +239,7 @@
 #define AM335X_INT_SPI1INT                        125	/* McSPI1  SINTERRUPTN */
 
 #define OMAP3_AM335X_NR_IRQ_VECTORS    125 
-#endif
+//#endif
 
 #ifndef __ASSEMBLY__
 
diff --git a/kernel/arch/earm/omap_padconf.c b/kernel/arch/earm/omap_padconf.c
index 3b6638a8b..2c8f52246 100644
--- a/kernel/arch/earm/omap_padconf.c
+++ b/kernel/arch/earm/omap_padconf.c
@@ -6,6 +6,7 @@
 #include <machine/cpu.h>
 #include <minix/mmio.h>
 #include <minix/padconf.h>
+#include <minix/board.h>
 #include <assert.h>
 #include <io.h>
 #include <stdlib.h>
@@ -18,25 +19,43 @@ struct omap_padconf
 	vir_bytes base;
 	vir_bytes offset;
 	vir_bytes size;
+	unsigned int board_filter_value;
+	unsigned int board_filter_mask;
 };
 
-static struct omap_padconf omap_padconf = {
-	.base = PADCONF_REGISTERS_BASE,
-	.offset = PADCONF_REGISTERS_OFFSET,
-	.size = PADCONF_REGISTERS_SIZE
+
+struct omap_padconf omap_padconfs[] = {
+  {
+	.base = PADCONF_DM37XX_REGISTERS_BASE,
+	.offset = PADCONF_DM37XX_REGISTERS_OFFSET,
+	.size = PADCONF_DM37XX_REGISTERS_SIZE,
+	.board_filter_value = BOARD_FILTER_BBXM_VALUE,
+	.board_filter_mask = BOARD_FILTER_BBXM_MASK,
+  },
+  {
+	.base = PADCONF_AM335X_REGISTERS_BASE,
+	.offset = PADCONF_AM335X_REGISTERS_OFFSET,
+	.size = PADCONF_AM335X_REGISTERS_SIZE,
+	.board_filter_value = BOARD_FILTER_BB_VALUE,
+	.board_filter_mask = BOARD_FILTER_BB_MASK,
+  },
 };
 
+/* initialized in init */
+static struct omap_padconf *omap_padconf;
+
+
 static kern_phys_map padconf_phys_map;
 
 int
 arch_padconf_set(u32_t padconf, u32_t mask, u32_t value)
 {
 	/* check that the value will be inside the padconf memory range */
-	if (padconf >= (PADCONF_REGISTERS_SIZE - PADCONF_REGISTERS_OFFSET)) {
+	if (padconf >= (omap_padconf->size - omap_padconf->offset)) {
 		return EINVAL;	/* outside of valid range */
 	}
 
-	set32(padconf + omap_padconf.base + omap_padconf.offset, mask, value);
+	set32(padconf + omap_padconf->base + omap_padconf->offset, mask, value);
 
 	return OK;
 }
@@ -44,8 +63,19 @@ arch_padconf_set(u32_t padconf, u32_t mask, u32_t value)
 void
 arch_padconf_init(void)
 {
-	kern_phys_map_ptr(omap_padconf.base, omap_padconf.size,
-	     &padconf_phys_map, (vir_bytes) &omap_padconf.base);
+	int x;
+	omap_padconf = NULL;
+	/* find the correct padconf */
+	for (x =0 ; x < sizeof(omap_padconfs)/sizeof(omap_padconfs[0]) ; x++){
+		if ( (omap_padconfs[x].board_filter_mask & machine.board_id) == omap_padconfs[x].board_filter_value){
+			omap_padconf = &omap_padconfs[x];
+			break;
+		}
+	}
+	assert(omap_padconf);
+		
+	kern_phys_map_ptr(omap_padconf->base, omap_padconf->size,
+	     &padconf_phys_map, (vir_bytes) &omap_padconf->base);
 
 	return;
 }
diff --git a/kernel/arch/earm/omap_reset.c b/kernel/arch/earm/omap_reset.c
index 29b059c97..5715679a8 100644
--- a/kernel/arch/earm/omap_reset.c
+++ b/kernel/arch/earm/omap_reset.c
@@ -2,6 +2,7 @@
 #include <sys/types.h>
 #include <machine/cpu.h>
 #include <minix/type.h>
+#include <minix/board.h>
 #include <io.h>
 
 #include "kernel/kernel.h"
@@ -11,21 +12,17 @@
 #include "arch_proto.h"
 #include "omap_reset.h"
 
-#ifdef AM335X
-#define CM_BASE 0x44E00000
-#define CM_SIZE 0x1000
-#define PRM_DEVICE_OFFSET 0xf00
-#define PRM_RSTCTRL_REG 0x00
-#define RST_GLOBAL_WARM_SW_BIT 0 
-#elif DM37XX
-#define CM_BASE 0x48307000
-#define CM_SIZE 0x1000
-#define PRM_RSTCTRL_REG 0x250
-#define RST_DPLL3_BIT 2
-#else
-#define CM_BASE 0x00000000
-#define CM_SIZE 0x1000
-#endif
+#define AM335X_CM_BASE 0x44E00000
+#define AM335X_CM_SIZE 0x1000
+
+#define AM335X_PRM_DEVICE_OFFSET 0xf00
+#define AM335X_PRM_RSTCTRL_REG 0x00
+#define AM335X_RST_GLOBAL_WARM_SW_BIT 0 
+
+#define DM37XX_CM_BASE 0x48307000
+#define DM37XX_CM_SIZE 0x1000
+#define DM37XX_PRM_RSTCTRL_REG 0x250
+#define DM37XX_RST_DPLL3_BIT 2
 
 struct omap_reset
 {
@@ -33,28 +30,32 @@ struct omap_reset
 	vir_bytes size;
 };
 
-static struct omap_reset omap_reset = {
-	.base = CM_BASE,
-	.size = CM_SIZE
-};
+static struct omap_reset omap_reset;
 
 static kern_phys_map reset_phys_map;
 
 void
 omap3_reset_init(void)
 {
-#if defined(AM335X) || defined(DM37XX)
+
+	if(BOARD_IS_BBXM(machine.board_id)){
+		omap_reset.base = DM37XX_CM_BASE;
+		omap_reset.size = DM37XX_CM_SIZE;
+	} else if(BOARD_IS_BB(machine.board_id)){
+		omap_reset.base = AM335X_CM_BASE;
+		omap_reset.size = AM335X_CM_SIZE;
+	}
+
 	kern_phys_map_ptr(omap_reset.base, omap_reset.size, &reset_phys_map,
 	    (vir_bytes) &omap_reset.base);
-#endif /* AM335X || DM37XX */
 }
 
 void
 omap3_reset(void)
 {
-#ifdef AM335X
-	mmio_set((omap_reset.base + PRM_DEVICE_OFFSET + PRM_RSTCTRL_REG), (1 << RST_GLOBAL_WARM_SW_BIT));
-#elif DM37XX
-	mmio_set((omap_reset.base + PRM_RSTCTRL_REG), (1 << RST_DPLL3_BIT));
-#endif
+	if(BOARD_IS_BBXM(machine.board_id)){
+		mmio_set((omap_reset.base + DM37XX_PRM_RSTCTRL_REG), (1 << DM37XX_RST_DPLL3_BIT));
+	} else if(BOARD_IS_BB(machine.board_id)){
+		mmio_set((omap_reset.base + AM335X_PRM_DEVICE_OFFSET + AM335X_PRM_RSTCTRL_REG), (1 << AM335X_RST_GLOBAL_WARM_SW_BIT));
+	}
 }
diff --git a/kernel/arch/earm/omap_timer.c b/kernel/arch/earm/omap_timer.c
index cb2c2a1ec..ec3e42a28 100644
--- a/kernel/arch/earm/omap_timer.c
+++ b/kernel/arch/earm/omap_timer.c
@@ -2,6 +2,7 @@
 #include "kernel/clock.h"
 #include <sys/types.h>
 #include <machine/cpu.h>
+#include <minix/board.h>
 #include <minix/mmio.h>
 #include <assert.h>
 #include <io.h>
@@ -157,37 +158,37 @@ void omap3_frclock_init(void)
 	&fr_timer_phys_map, (vir_bytes) &fr_timer.base);
 
     /* enable the clock */
-#ifdef AM335X
-    /* Disable the module and wait for the module to be disabled */
-    set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK,CM_MODULEMODE_DISABLED);
-    while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_DISABLE);
+    if(BOARD_IS_BBXM(machine.board_id)){
+	    /* Stop timer */
+	    mmio_clear(fr_timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
 
-    set32(CLKSEL_TIMER7_CLK,CLKSEL_TIMER7_CLK_SEL_MASK, CLKSEL_TIMER7_CLK_SEL_SEL2);
-    while( (read32(CLKSEL_TIMER7_CLK) & CLKSEL_TIMER7_CLK_SEL_MASK) != CLKSEL_TIMER7_CLK_SEL_SEL2);
+	    /* Use functional clock source for GPTIMER10 */
+	    mmio_set(OMAP3_CM_CLKSEL_CORE, OMAP3_CLKSEL_GPT10);
 
-    /* enable the module and wait for the module to be ready */
-    set32(CM_PER_TIMER7_CLKCTRL,CM_MODULEMODE_MASK,CM_MODULEMODE_ENABLE);
-    while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_FUNC);
-#endif
+	    /* Scale timer down to 13/8 = 1.625 Mhz to roughly get microsecond ticks */
+	    /* The scale is computed as 2^(PTV+1). So if PTV == 2, we get 2^3 = 8.
+	     */
+	    mmio_set(fr_timer.base + fr_timer.regs->TCLR, (2 << OMAP3_TCLR_PTV));
+    } else if(BOARD_IS_BB(machine.board_id)){
+	    /* Disable the module and wait for the module to be disabled */
+	    set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK,CM_MODULEMODE_DISABLED);
+	    while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_DISABLE);
 
-    /* Stop timer */
-    mmio_clear(fr_timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
+	    set32(CLKSEL_TIMER7_CLK,CLKSEL_TIMER7_CLK_SEL_MASK, CLKSEL_TIMER7_CLK_SEL_SEL2);
+	    while( (read32(CLKSEL_TIMER7_CLK) & CLKSEL_TIMER7_CLK_SEL_MASK) != CLKSEL_TIMER7_CLK_SEL_SEL2);
+
+	    /* enable the module and wait for the module to be ready */
+	    set32(CM_PER_TIMER7_CLKCTRL,CM_MODULEMODE_MASK,CM_MODULEMODE_ENABLE);
+	    while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_FUNC);
+
+	    /* Stop timer */
+	    mmio_clear(fr_timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
+
+	   /* 24Mhz / 16 = 1.5 Mhz */
+	    mmio_set(fr_timer.base + fr_timer.regs->TCLR, (3 << OMAP3_TCLR_PTV));
+    }
 
-#ifdef DM37XX
-    /* Use functional clock source for GPTIMER10 */
-    mmio_set(OMAP3_CM_CLKSEL_CORE, OMAP3_CLKSEL_GPT10);
-#endif
 
-#ifdef DM37XX
-    /* Scale timer down to 13/8 = 1.625 Mhz to roughly get microsecond ticks */
-    /* The scale is computed as 2^(PTV+1). So if PTV == 2, we get 2^3 = 8.
-     */
-    mmio_set(fr_timer.base + fr_timer.regs->TCLR, (2 << OMAP3_TCLR_PTV));
-#endif
-#ifdef AM335X
-   /* 24Mhz / 16 = 1.5 Mhz */
-    mmio_set(fr_timer.base + fr_timer.regs->TCLR, (3 << OMAP3_TCLR_PTV));
-#endif
 
     /* Start and auto-reload at 0 */
     mmio_write(fr_timer.base + fr_timer.regs->TLDR, 0x0);
@@ -230,11 +231,15 @@ void omap3_timer_init(unsigned freq)
     /* enable the module and wait for the module to be ready */
     set32(CM_WKUP_TIMER1_CLKCTRL,CM_MODULEMODE_MASK,CM_MODULEMODE_ENABLE);
     while( (mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_FUNC);
+
+    /* Stop timer */
+    mmio_clear(timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
 #endif
+
+#ifdef DM37XX
     /* Stop timer */
     mmio_clear(timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
 
-#ifdef DM37XX
     /* Use 32 KHz clock source for GPTIMER1 */
     mmio_clear(OMAP3_CM_CLKSEL_WKUP, OMAP3_CLKSEL_GPT1);
 #endif
diff --git a/kernel/arch/earm/omap_timer_registers.h b/kernel/arch/earm/omap_timer_registers.h
index 42e55b190..ce84f869b 100644
--- a/kernel/arch/earm/omap_timer_registers.h
+++ b/kernel/arch/earm/omap_timer_registers.h
@@ -1,7 +1,7 @@
 #ifndef _OMAP_TIMER_REGISTERS_H
 #define _OMAP_TIMER_REGISTERS_H
 
-#ifdef DM37XX
+//#ifdef DM37XX
 
 /* General-purpose timer register map */
 #define OMAP3_GPTIMER1_BASE  0x48318000 /* GPTIMER1 physical address */
@@ -16,7 +16,7 @@
 #define OMAP3_GPTIMER10_BASE 0x48086000 /* GPTIMER10 physical address */
 #define OMAP3_GPTIMER11_BASE 0x48088000 /* GPTIMER11 physical address */
 
-#endif /* DM37XX */
+//#endif /* DM37XX */
 
 /* General-purpose timer registers */
 #define OMAP3_TIMER_TIDR      0x000 /* IP revision code */
@@ -40,7 +40,7 @@
 #define OMAP3_TIMER_TOCR      0x054 /* Masks tick interrupt */
 #define OMAP3_TIMER_TOWR      0x058 /* Number of masked overflow interrupts */
 
-#ifdef AM335X
+//#ifdef AM335X
 #define AM335X_DMTIMER0_BASE      0x44E05000  /* DMTimer0 Registers */
 #define AM335X_DMTIMER1_1MS_BASE  0x44E31000 /* DMTimer1 1ms Registers (Accurate 1ms timer) */
 #define AM335X_DMTIMER2_BASE      0x48040000 /*  DMTimer2 Registers */
@@ -68,7 +68,7 @@
 #define AM335X_TIMER_TSICR     0x054 /* Control posted mode and functional SW reset */
 #define AM335X_TIMER_TCAR2     0x058 /* Second captured value of counter register */
 
-#endif
+//#endif
 
 
 /* Interrupt status register fields */
@@ -88,7 +88,7 @@
 #define OMAP3_TCLR_PTV      2
 #define OMAP3_TCLR_OVF_TRG  (1 << 10) /* Overflow trigger */
 
-#ifdef DM37XX
+//#ifdef DM37XX
 
 #define OMAP3_CM_CLKSEL_GFX		0x48004b40
 #define OMAP3_CM_CLKEN_PLL		0x48004d00
@@ -98,7 +98,7 @@
 #define OMAP3_CM_CLKSEL_PER		0x48005040
 #define OMAP3_CM_CLKSEL_WKUP    0x48004c40 /* GPT1 source clock selection */
 
-#endif /* DM37XX */
+//#endif /* DM37XX */
 
 #ifdef AM335X
 
diff --git a/kernel/arch/earm/pre_init.c b/kernel/arch/earm/pre_init.c
index 7360bd661..3b8ccfb73 100644
--- a/kernel/arch/earm/pre_init.c
+++ b/kernel/arch/earm/pre_init.c
@@ -277,6 +277,71 @@ void get_parameters(u32_t ebx, kinfo_t *cbi)
 	}
 }
 
+
+
+
+#define OMAP3_ROM_ADDRESS 0x40000000
+#define OMAP3_ROM_SIZE 0x00020000
+
+
+struct omap_rom_sum {
+	u32_t sum,
+	u32_t board_id,
+	
+} ;
+
+static struct  omap_rom_sum[] = {
+	{ .sum = 0x2185, .board_id = BOARD_ID_BBW };
+}
+
+void determine_omap_board_id(){
+	/* for am335x read 0x44E10600 */
+	//27-12  (See AM335x errata for specific information on each revision.)
+	//11-1  (Device part number 0xB944)
+
+
+        /*
+        * 16-bit checksum, rotating right before each addition;
+        * overflow is discarded.
+        */
+        u_char *p;
+	u32_t count = 0;
+        u_int lcrc = 0;
+	p = (char *) OMAP3_ROM_ADDRESS;
+	
+        for (count =0 ; count < OMAP3_ROM_SIZE ; count++){
+		if (lcrc & 1) { lcrc |= 0x10000; }
+		lcrc = ((lcrc >> 1) + *p) & 0xffff;
+		p++;
+        }
+	/* calculate a BSD compatible checksum of the rom code */
+	printf("ROM sum 0x%04x\n",lcrc);
+}
+
+void determine_board_id(){
+
+	u32_t midr = read_midr();
+	u32_t impl = (midr & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT;
+	u32_t major = (midr & MIDR_MAJOR_REV_MASK) >> MIDR_MAJOR_REV_SHIFT;
+	u32_t arch_code = (midr & MIDR_ARCH_CODE_MASK) >> MIDR_ARCH_CODE_SHIFT;
+	u32_t part_nr = (midr & MIDR_PART_NUMBER_MASK) >> MIDR_PART_NUMBER_SHIFT;
+	u32_t minor = (midr & MIDR_MINOR_REV_MASK) >> MIDR_MINOR_REV_SHIFT;
+
+
+	/* ARMv7 Must have 0x41 as implementer code */
+	assert(impl == 0x41); 
+	
+	/* if arch code equals 0xf we need to read out the cpuid register */
+	if (arch_code == 0xf){ 
+
+	}
+	printf("ID 0x%08x\n",midr);
+	printf("ID IMPL MASKED%08x\n",midr & MIDR_IMPLEMENTER_MASK);
+	
+	printf(" IMPL= 0x%x\nmajor= 0x%x\nminor= 0x%x\n arch_code= 0x%0x\n part_nr= 0x%0x\n",impl,major,minor,arch_code,part_nr);
+	determine_omap_board_id();	
+}
+
 kinfo_t *pre_init(u32_t magic, u32_t ebx)
 {
 	/* Clear BSS */
@@ -287,6 +352,7 @@ kinfo_t *pre_init(u32_t magic, u32_t ebx)
 	 * Here we find out whether we should do serial output.
 	 */
 	get_parameters(ebx, &kinfo);
+	determine_board_id();
 
 	/* Make and load a pagetable that will map the kernel
 	 * to where it should be; but first a 1:1 mapping so
@@ -314,3 +380,4 @@ void busy_delay_ms(int x) { }
 int raise(int n) { panic("raise(%d)\n", n); }
 int kern_phys_map_ptr( phys_bytes base_address, vir_bytes io_size, 
 	struct kern_phys_map * priv, vir_bytes ptr) {};
+struct machine machine;