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26
sys/Makefile
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@ -1,26 +0,0 @@
# $NetBSD: Makefile,v 1.79 2013/03/01 18:25:27 joerg Exp $
.include <bsd.own.mk>
SUBDIR= altq arch dev fs \
net net80211 netatalk netinet netinet6 \
netmpls \
sys ufs uvm
.if !defined(__MINIX)
# interrupt implementation depends on the kernel within the port
#.if (${MACHINE} != "evbppc")
.if make(obj) || make(cleandir) || ${MKKMOD} != "no"
SUBDIR+=modules
.endif
#.endif
.endif # !defined(__MINIX)
# LSC FIXME: Remove this test as soon as we have imported RUMP
.if !defined(__MINIX)
.if make(includes) || make(obj) || make(cleandir)
SUBDIR+= rump
.endif
.endif # !defined(__MINIX)
.include <bsd.kinc.mk>

11
sys/altq/Makefile
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# $NetBSD: Makefile,v 1.3 2006/10/12 19:59:08 peter Exp $
INCSDIR= /usr/include/altq
INCS= \
\
\
\
if_altq.h
.include <bsd.kinc.mk>

177
sys/altq/if_altq.h
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/* $NetBSD: if_altq.h,v 1.14 2014/07/01 10:16:02 ozaki-r Exp $ */
/* $KAME: if_altq.h,v 1.12 2005/04/13 03:44:25 suz Exp $ */
/*
* Copyright (C) 1997-2003
* Sony Computer Science Laboratories Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY SONY CSL AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL SONY CSL OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ALTQ_IF_ALTQ_H_
#define _ALTQ_IF_ALTQ_H_
#if defined(_KERNEL_OPT)
#include "opt_altq_enabled.h"
#endif
struct altq_pktattr; struct tb_regulator; struct top_cdnr;
/*
* Structure defining a queue for a network interface.
*/
struct ifaltq {
/* fields compatible with struct ifqueue */
struct mbuf *ifq_head;
struct mbuf *ifq_tail;
int ifq_len;
int ifq_maxlen;
int ifq_drops;
kmutex_t *ifq_lock;
/* alternate queueing related fields */
int altq_type; /* discipline type */
int altq_flags; /* flags (e.g. ready, in-use) */
void *altq_disc; /* for discipline-specific use */
struct ifnet *altq_ifp; /* back pointer to interface */
int (*altq_enqueue)(struct ifaltq *, struct mbuf *,
struct altq_pktattr *);
struct mbuf *(*altq_dequeue)(struct ifaltq *, int);
int (*altq_request)(struct ifaltq *, int, void *);
/* classifier fields */
void *altq_clfier; /* classifier-specific use */
void *(*altq_classify)(void *, struct mbuf *, int);
/* token bucket regulator */
struct tb_regulator *altq_tbr;
/* input traffic conditioner (doesn't belong to the output queue...) */
struct top_cdnr *altq_cdnr;
};
#ifdef _KERNEL
/*
* packet attributes used by queueing disciplines.
* pattr_class is a discipline-dependent scheduling class that is
* set by a classifier.
* pattr_hdr and pattr_af may be used by a discipline to access
* the header within a mbuf. (e.g. ECN needs to update the CE bit)
* note that pattr_hdr could be stale after m_pullup, though link
* layer output routines usually don't use m_pullup. link-level
* compression also invalidates these fields. thus, pattr_hdr needs
* to be verified when a discipline touches the header.
*/
struct altq_pktattr {
void *pattr_class; /* sched class set by classifier */
int pattr_af; /* address family */
void * pattr_hdr; /* saved header position in mbuf */
};
/*
* mbuf tag to carry a queue id (and hints for ECN).
*/
struct altq_tag {
u_int32_t qid; /* queue id */
/* hints for ecn */
int af; /* address family */
void *hdr; /* saved header position in mbuf */
};
/*
* a token-bucket regulator limits the rate that a network driver can
* dequeue packets from the output queue.
* modern cards are able to buffer a large amount of packets and dequeue
* too many packets at a time. this bursty dequeue behavior makes it
* impossible to schedule packets by queueing disciplines.
* a token-bucket is used to control the burst size in a device
* independent manner.
*/
struct tb_regulator {
int64_t tbr_rate; /* (scaled) token bucket rate */
int64_t tbr_depth; /* (scaled) token bucket depth */
int64_t tbr_token; /* (scaled) current token */
int64_t tbr_filluptime; /* (scaled) time to fill up bucket */
u_int64_t tbr_last; /* last time token was updated */
int tbr_lastop; /* last dequeue operation type
needed for poll-and-dequeue */
};
/* if_altqflags */
#define ALTQF_READY 0x01 /* driver supports alternate queueing */
#define ALTQF_ENABLED 0x02 /* altq is in use */
#define ALTQF_CLASSIFY 0x04 /* classify packets */
#define ALTQF_CNDTNING 0x08 /* altq traffic conditioning is enabled */
#define ALTQF_DRIVER1 0x40 /* driver specific */
/* if_altqflags set internally only: */
#define ALTQF_CANTCHANGE (ALTQF_READY)
/* altq_dequeue 2nd arg */
#define ALTDQ_REMOVE 1 /* dequeue mbuf from the queue */
#define ALTDQ_POLL 2 /* don't dequeue mbuf from the queue */
/* altq request types (currently only purge is defined) */
#define ALTRQ_PURGE 1 /* purge all packets */
#define ALTQ_IS_READY(ifq) ((ifq)->altq_flags & ALTQF_READY)
#define ALTQ_IS_ENABLED(ifq) ((ifq)->altq_flags & ALTQF_ENABLED)
#define ALTQ_NEEDS_CLASSIFY(ifq) ((ifq)->altq_flags & ALTQF_CLASSIFY)
#define ALTQ_IS_CNDTNING(ifq) ((ifq)->altq_flags & ALTQF_CNDTNING)
#define ALTQ_SET_CNDTNING(ifq) ((ifq)->altq_flags |= ALTQF_CNDTNING)
#define ALTQ_CLEAR_CNDTNING(ifq) ((ifq)->altq_flags &= ~ALTQF_CNDTNING)
#define ALTQ_IS_ATTACHED(ifq) ((ifq)->altq_disc != NULL)
#define ALTQ_ENQUEUE(ifq, m, pa, err) \
(err) = (*(ifq)->altq_enqueue)((ifq),(m),(pa))
#define ALTQ_DEQUEUE(ifq, m) \
(m) = (*(ifq)->altq_dequeue)((ifq), ALTDQ_REMOVE)
#define ALTQ_POLL(ifq, m) \
(m) = (*(ifq)->altq_dequeue)((ifq), ALTDQ_POLL)
#define ALTQ_PURGE(ifq) \
(void)(*(ifq)->altq_request)((ifq), ALTRQ_PURGE, (void *)0)
#define ALTQ_IS_EMPTY(ifq) ((ifq)->ifq_len == 0)
#define TBR_IS_ENABLED(ifq) ((ifq)->altq_tbr != NULL)
extern int altq_attach(struct ifaltq *, int, void *,
int (*)(struct ifaltq *, struct mbuf *,
struct altq_pktattr *),
struct mbuf *(*)(struct ifaltq *, int),
int (*)(struct ifaltq *, int, void *),
void *,
void *(*)(void *, struct mbuf *, int));
extern int altq_detach(struct ifaltq *);
extern int altq_enable(struct ifaltq *);
extern int altq_disable(struct ifaltq *);
extern struct mbuf *tbr_dequeue(struct ifaltq *, int);
extern int (*altq_input)(struct mbuf *, int);
#if 1 /* ALTQ3_CLFIER_COMPAT */
void altq_etherclassify(struct ifaltq *, struct mbuf *, struct altq_pktattr *);
#endif
#endif /* _KERNEL */
#endif /* _ALTQ_IF_ALTQ_H_ */

78
sys/arch/Makefile
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# $NetBSD: Makefile,v 1.45 2014/09/03 19:27:53 matt Exp $
# For now, we install the machine and arch includes, and symlink 'machine'
# to the location of the machine includes (usually).
#
# Eventually, we should install everything.
.include <bsd.own.mk>
ARCHSUBDIR= ${MACHINE_CPU}
.if ${ARCHSUBDIR} == "mips64"
ARCHSUBDIR= mips
.endif
.if ${ARCHSUBDIR} == "powerpc64"
ARCHSUBDIR= powerpc
.endif
.if ${MACHINE_CPU} == "aarch64"
SUBDIR= evbarm64
.elif ${MACHINE_CPU} == "arm"
.if defined(__MINIX)
SUBDIR= evbarm
.else
SUBDIR= acorn26 acorn32 cats epoc32 evbarm hpcarm iyonix netwinder shark zaurus
.endif # defined(__MINIX)
.else
SUBDIR= ${MACHINE}
.endif
.if ${MACHINE} != ${ARCHSUBDIR}
.if exists(${ARCHSUBDIR})
SUBDIR+= ${ARCHSUBDIR}
.endif
.endif
.if ${MACHINE_CPU} == "aarch64"
SUBDIR+= arm
.endif
.if ${MACHINE} == sparc
SUBDIR+= sparc64
.endif
.if (${MACHINE} == hpcmips || ${MACHINE} == hpcsh)
SUBDIR+= hpc
.endif
.if (${MACHINE} == sun2 || ${MACHINE} == sun3)
SUBDIR+= sun68k
.endif
.if defined(XEN_BUILD)
SUBDIR+= xen
.endif
#SUBDIR=aarch64 acorn26 acorn32 algor alpha amiga amigappc arm arc atari \
# bebox \
# cats cesfic cobalt \
# dreamcast \
# emips epoc32 evbarm evbmips evbppc evbsh3 ews4800mips\
# hp300 hpc hpcarm hpcmips hpcsh \
# i386 iyonix \
# luna68k \
# m68k mac68k macppc mips mipsco mmeye mvme68k \
# netwinder news68k newsmips next68k \
# ofppc or1k \
# playstation2 pmax powerpc prep \
# sandpoint sbmips sgimips sh3 shark sparc sparc64 sun2 sun3 sun68k \
# rs6000 \
# vax \
# x68k x86_64 xen \
# zaurus
.if ${MACHINE_CPU} == aarch64 || ${MACHINE_CPU} == "arm"
INCSYMLINKS= ${MACHINE_CPU} /usr/include/machine
.else
INCSYMLINKS= ${MACHINE} /usr/include/machine
.endif
INCSYMLINKS+= machine/float.h /usr/include/float.h
.include <bsd.kinc.mk>

10
sys/arch/arm/Makefile
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# $NetBSD: Makefile,v 1.8 2008/06/25 03:33:39 matt Exp $
SUBDIR= include .WAIT include/arm26 include/arm32
.ifndef __MINIX
# install footbridge headers.
SUBDIR+= footbridge
.endif
.include <bsd.kinc.mk>

23
sys/arch/arm/Makefile.inc
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@ -1,23 +0,0 @@
# $NetBSD: Makefile.inc,v 1.1 2011/04/04 19:43:34 dyoung Exp $
AARM= ${SYSDIR}/arch/arm/arm/*.S
SARM= ${SYSDIR}/arch/arm/arm/*.[ch] ${SYSDIR}/arch/arm/include/*.h
SARM+= ${SYSDIR}/arch/arm/arm32/*.[ch]
SARM+= ${SYSDIR}/arch/arm/at91/*.[ch]
SARM+= ${SYSDIR}/arch/arm/ep93xx/*.[ch]
SARM+= ${SYSDIR}/arch/arm/footbridge/*.[ch]
SARM+= ${SYSDIR}/arch/arm/fpe-arm/*.[ch]
SARM+= ${SYSDIR}/arch/arm/gemini/*.[ch]
SARM+= ${SYSDIR}/arch/arm/imx/*.[ch]
SARM+= ${SYSDIR}/arch/arm/iomd/*.[ch]
SARM+= ${SYSDIR}/arch/arm/ixp12x0/*.[ch]
SARM+= ${SYSDIR}/arch/arm/mainbus/*.[ch]
SARM+= ${SYSDIR}/arch/arm/marvell/*.[ch]
SARM+= ${SYSDIR}/arch/arm/mpcore/*.[ch]
SARM+= ${SYSDIR}/arch/arm/ofw/*.[ch]
SARM+= ${SYSDIR}/arch/arm/omap/*.[ch]
SARM+= ${SYSDIR}/arch/arm/pic/*.[ch]
SARM+= ${SYSDIR}/arch/arm/s3c2xx0/*.[ch]
SARM+= ${SYSDIR}/arch/arm/sa11x0/*.[ch]
SARM+= ${SYSDIR}/arch/arm/vfp/*.[ch]
SARM+= ${SYSDIR}/arch/arm/xscale/*.[ch]

25
sys/arch/arm/include/Makefile
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# $NetBSD: Makefile,v 1.49 2014/07/23 18:19:43 alnsn Exp $
INCSDIR= /usr/include/arm
INCS= aeabi.h ansi.h aout_machdep.h apmvar.h armreg.h asm.h atomic.h \
bswap.h byte_swap.h \
cdefs.h cpu.h cpuconf.h \
disklabel.h \
elf_machdep.h endian.h endian_machdep.h \
fenv.h float.h frame.h \
ieee.h ieeefp.h \
int_const.h int_fmtio.h int_limits.h int_mwgwtypes.h int_types.h \
joystick.h \
kcore.h \
limits.h lock.h \
math.h mcontext.h mutex.h \
param.h pcb.h pmc.h proc.h profile.h rwlock.h \
ptrace.h \
reg.h rwlock.h \
setjmp.h signal.h sljit_machdep.h swi.h sysarch.h \
trap.h types.h \
vfpreg.h vmparam.h \
wchar_limits.h
.include <bsd.kinc.mk>

26
sys/arch/arm/include/Makefile.common
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# $NetBSD: Makefile.common,v 1.2 2013/05/02 03:56:40 matt Exp $
.PATH: ../../arm/include/common
.if 0
INCS+= ansi.h aout_machdep.h asm.h \
bswap.h \
cdefs.h cpu.h \
elf_machdep.h endian.h endian_machdep.h \
fenv.h float.h frame.h \
ieee.h ieeefp.h \
int_const.h int_fmtio.h int_limits.h int_mwgwtypes.h int_types.h \
limits.h lock.h \
math.h mcontext.h mutex.h \
param.h pcb.h pmap.h pmc.h proc.h profile.h ptrace.h \
reg.h rwlock.h \
setjmp.h signal.h sysarch.h \
trap.h types.h \
vmparam.h \
wchar_limits.h
.else
INCS+= disklabel.h \
intr.h
.endif
.include <bsd.kinc.mk>

5
sys/arch/arm/include/Makefile.inc
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# $NetBSD: Makefile.inc,v 1.2 2015/02/22 17:38:19 riastradh Exp $
.if !defined(RUMPKERNEL)
CFLAGS+= -mfloat-abi=soft
.endif

207
sys/arch/arm/include/aeabi.h
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/* $NetBSD: aeabi.h,v 1.5 2013/08/01 22:20:40 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_AEABI_H_
#define _ARM_AEABI_H_
#if defined(_KERNEL) || defined(_STANDALONE)
#include <sys/types.h>
#else
#include <stddef.h>
#endif
#define __value_in_regs /* nothing */
#define __aapcs __attribute__((__pcs__("aapcs")))
/*
* Standard double precision floating-point arithmetic helper functions
*/
double __aeabi_dadd(double, double) __aapcs; // double-precision addition
double __aeabi_ddiv(double n, double d) __aapcs; // double-precision division, n / d
double __aeabi_dmul(double, double) __aapcs; // double-precision multiplication
double __aeabi_drsub(double x, double y) __aapcs; // double-precision reverse subtraction, y - x
double __aeabi_dsub(double x, double y) __aapcs; // double-precision subtraction, x - y
double __aeabi_dneg(double) __aapcs; // double-precision negation (obsolete, to be removed in r2.09)
/*
* Double precision floating-point comparison helper functions
*/
void __aeabi_cdcmpeq(double, double) __aapcs; // non-excepting equality comparison [1], result in PSR ZC flags
void __aeabi_cdcmple(double, double) __aapcs; // 3-way (<, =, >) compare [1], result in PSR ZC flags
void __aeabi_cdrcmple(double, double) __aapcs; // reversed 3-way (<, =, >) compare [1], result in PSR ZC flags
int __aeabi_dcmpeq(double, double) __aapcs; // result (1, 0) denotes (=, <>) [2], use for C == and !=
int __aeabi_dcmplt(double, double) __aapcs; // result (1, 0) denotes (<, >=) [2], use for C <
int __aeabi_dcmple(double, double) __aapcs; // result (1, 0) denotes (<=, >) [2], use for C <=
int __aeabi_dcmpge(double, double) __aapcs; // result (1, 0) denotes (>=, <) [2], use for C >=
int __aeabi_dcmpgt(double, double) __aapcs; // result (1, 0) denotes (>, <=) [2], use for C >
int __aeabi_dcmpun(double, double) __aapcs; // result (1, 0) denotes (?, <=>) [2], use for C99 isunordered()
/*
* Standard single precision floating-point arithmetic helper functions
*/
float __aeabi_fadd(float, float) __aapcs; // single-precision addition
float __aeabi_fdiv(float n, float d) __aapcs; // single-precision division, n / d
float __aeabi_fmul(float, float) __aapcs; // single-precision multiplication
float __aeabi_frsub(float x, float y) __aapcs; // single-precision reverse subtraction, y - x
float __aeabi_fsub(float x, float y) __aapcs; // single-precision subtraction, x - y
float __aeabi_fneg(float) __aapcs; // single-precision negation (obsolete, to be removed in r2.09)
/*
* Standard single precision floating-point comparison helper functions
*/
void __aeabi_cfcmpeq(float, float) __aapcs; // non-excepting equality comparison [1], result in PSR ZC flags
void __aeabi_cfcmple(float, float) __aapcs; // 3-way (<, =, ?>) compare [1], result in PSR ZC flags
void __aeabi_cfrcmple(float, float) __aapcs; // reversed 3-way (<, =, ?>) compare [1], result in PSR ZC flags
int __aeabi_fcmpeq(float, float) __aapcs; // result (1, 0) denotes (=, <>) [2], use for C == and !=
int __aeabi_fcmplt(float, float) __aapcs; // result (1, 0) denotes (<, >=) [2], use for C <
int __aeabi_fcmple(float, float) __aapcs; // result (1, 0) denotes (<=, >) [2], use for C <=
int __aeabi_fcmpge(float, float) __aapcs; // result (1, 0) denotes (>=, <) [2], use for C >=
int __aeabi_fcmpgt(float, float) __aapcs; // result (1, 0) denotes (>, <=) [2], use for C >
int __aeabi_fcmpun(float, float) __aapcs; // result (1, 0) denotes (?, <=>) [2], use for C99 isunordered()
/*
* Standard conversions between floating types
*/
float __aeabi_d2f(double) __aapcs; // double to float (single precision) conversion
double __aeabi_f2d(float) __aapcs; // float (single precision) to double conversion
float __aeabi_h2f(short hf) __aapcs; // IEEE 754 binary16 storage format (VFP half precision) to binary32 (float) conversion [4, 5]
short __aeabi_f2h(float f) __aapcs; // IEEE 754 binary32 (float) to binary16 storage format (VFP half precision) conversion [4, 6]
float __aeabi_h2f_alt(short hf) __aapcs; // __aeabi_h2f_alt converts from VFP alternative format [7].
short __aeabi_f2h_alt(float f) __aapcs; // __aeabi_f2h_alt converts to VFP alternative format [8].
/*
* Standard floating-point to integer conversions
*/
int __aeabi_d2iz(double) __aapcs; // double to integer C-style conversion [3]
unsigned __aeabi_d2uiz(double) __aapcs; // double to unsigned C-style conversion [3]
long long __aeabi_d2lz(double) __aapcs; // double to long long C-style conversion [3]
unsigned long long __aeabi_d2ulz(double) __aapcs; // double to unsigned long long C-style conversion [3]
int __aeabi_f2iz(float) __aapcs; // float (single precision) to integer C-style conversion [3]
unsigned __aeabi_f2uiz(float) __aapcs; // float (single precision) to unsigned C-style conversion [3]
long long __aeabi_f2lz(float) __aapcs; // float (single precision) to long long C-style conversion [3]
unsigned long long __aeabi_f2ulz(float) __aapcs; // float to unsigned long long C-style conversion [3]
/*
* Standard integer to floating-point conversions
*/
double __aeabi_i2d(int) __aapcs; // integer to double conversion
double __aeabi_ui2d(unsigned) __aapcs; // unsigned to double conversion
double __aeabi_l2d(long long) __aapcs; // long long to double conversion
double __aeabi_ul2d(unsigned long long) __aapcs; // unsigned long long to double conversion
float __aeabi_i2f(int) __aapcs; // integer to float (single precision) conversion
float __aeabi_ui2f(unsigned) __aapcs; // unsigned to float (single precision) conversion
float __aeabi_l2f(long long) __aapcs; // long long to float (single precision) conversion
float __aeabi_ul2f(unsigned long long) __aapcs; // unsigned long long to float (single precision) conversion
/*
* Long long functions
*/
long long __aeabi_lmul(long long, long long); // multiplication
/*
* A pair of (unsigned) long longs is returned in {{r0, r1}, {r2, r3}},
* the quotient in {r0, r1}, and the remainder in {r2, r3}.
*/
typedef struct { long long quot; long long rem; } lldiv_t;
__value_in_regs lldiv_t __aeabi_ldivmod(long long n, long long d); // signed long long division and remainder, {q, r} = n / d [2]
typedef struct { unsigned long long quot; unsigned long long rem; } ulldiv_t;
__value_in_regs ulldiv_t __aeabi_uldivmod(unsigned long long n, unsigned long long d); // unsigned signed ll division, remainder, {q, r} = n / d [2]
/*
* Because of 2's complement number representation, these functions work
* identically with long long replaced uniformly by unsigned long long.
* Each returns its result in {r0, r1}, as specified by the [AAPCS].
*/
long long __aeabi_llsl(long long, int); // logical shift left [1]
long long __aeabi_llsr(long long, int); // logical shift right [1]
long long __aeabi_lasr(long long, int); // arithmetic shift right [1]
/*
* The comparison functions return negative, zero, or a positive integer
* according to whether the comparison result is <, ==, or >, respectively
* (like strcmp).
*/
int __aeabi_lcmp(long long, long long); // signed long long comparison
int __aeabi_ulcmp(unsigned long long, unsigned long long); // unsigned long long comparison
int __aeabi_idiv(int numerator, int denominator);
unsigned __aeabi_uidiv(unsigned numerator, unsigned denominator);
typedef struct { int quot, rem; } idiv_return;
typedef struct { unsigned int quot, rem; } uidiv_return;
__value_in_regs idiv_return __aeabi_idivmod(int, int);
__value_in_regs uidiv_return __aeabi_uidivmod(unsigned int, unsigned int);
/*
* Division by zero
*
* If an integer or long long division helper function is called upon to
* divide by 0, it should return as quotient the value returned by a call
* to __aeabi_idiv0 or __aeabi_ldiv0, respectively. A *divmod helper should
* return as remainder either 0 or the original numerator.
*/
int __aeabi_idiv0(int);
long long __aeabi_ldiv0(long long);
/*
* These functions read and write 4-byte and 8-byte values at arbitrarily
* aligned addresses. Write functions return the value written,
* read functions the value read.
*/
int __aeabi_uread4(void *);
int __aeabi_uwrite4(int, void *);
long long __aeabi_uread8(void *);
long long __aeabi_uwrite8(long long, void *);
/*
* Memory copying, clearing, and setting
*/
void __aeabi_memcpy8(void *, const void *, size_t);
void __aeabi_memcpy4(void *, const void *, size_t);
void __aeabi_memcpy(void *, const void *, size_t);
void __aeabi_memmove8(void *, const void *, size_t);
void __aeabi_memmove4(void *, const void *, size_t);
void __aeabi_memmove(void *, const void *, size_t);
/*
* Memory clearing and setting
*/
void __aeabi_memset8(void *, size_t, int);
void __aeabi_memset4(void *, size_t, int);
void __aeabi_memset(void *, size_t, int);
void __aeabi_memclr8(void *, size_t);
void __aeabi_memclr4(void *, size_t);
void __aeabi_memclr(void *, size_t);
void *__aeabi_read_tp(void); // return the value of $tp
#undef __aapcs
#endif /* _ARM_AEABI_H_ */

79
sys/arch/arm/include/ansi.h
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@ -1,79 +0,0 @@
/* $NetBSD: ansi.h,v 1.17 2014/02/24 16:57:57 christos Exp $ */
/*
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)ansi.h 8.2 (Berkeley) 1/4/94
*/
#ifndef _ARM_ANSI_H_
#define _ARM_ANSI_H_
#include <sys/cdefs.h>
#include <machine/int_types.h>
/*
* Types which are fundamental to the implementation and may appear in
* more than one standard header are defined here. Standard headers
* then use:
* #ifdef _BSD_SIZE_T_
* typedef _BSD_SIZE_T_ size_t;
* #undef _BSD_SIZE_T_
* #endif
*/
#define _BSD_CLOCK_T_ unsigned int /* clock() */
#ifdef __PTRDIFF_TYPE__
#define _BSD_PTRDIFF_T_ __PTRDIFF_TYPE__ /* ptr1 - ptr2 */
#define _BSD_SSIZE_T_ __PTRDIFF_TYPE__ /* byte count or error */
#else
#define _BSD_PTRDIFF_T_ long int /* ptr1 - ptr2 */
#define _BSD_SSIZE_T_ long int /* byte count or error */
#endif
#ifdef __SIZE_TYPE__
#define _BSD_SIZE_T_ __SIZE_TYPE__ /* sizeof() */
#else
#define _BSD_SIZE_T_ unsigned long int /* sizeof() */
#endif
#define _BSD_TIME_T_ __int64_t /* time() */
#define _BSD_CLOCKID_T_ int /* clockid_t */
#define _BSD_TIMER_T_ int /* timer_t */
#define _BSD_SUSECONDS_T_ int /* suseconds_t */
#define _BSD_USECONDS_T_ unsigned int /* useconds_t */
#ifdef __WCHAR_TYPE__
#define _BSD_WCHAR_T_ __WCHAR_TYPE__ /* wchar_t */
#else
#define _BSD_WCHAR_T_ int /* wchar_t */
#endif
#ifdef __WINT_TYPE__
#define _BSD_WINT_T_ __WINT_TYPE__ /* wint_t */
#else
#define _BSD_WINT_T_ int /* wint_t */
#endif
#endif /* _ARM_ANSI_H_ */

59
sys/arch/arm/include/aout_machdep.h
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@ -1,59 +0,0 @@
/* $NetBSD: aout_machdep.h,v 1.7 2014/02/24 16:57:57 christos Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* 4. The name of the author may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ARM_AOUT_MACHDEP_H_
#define _ARM_AOUT_MACHDEP_H_
#define AOUT_LDPGSZ 4096
/* Relocation format. */
struct relocation_info_arm6 {
int r_address; /* offset in text or data segment */
unsigned r_symbolnum:24;/* ordinal number of add symbol */
unsigned r_pcrel:1; /* 1 if value should be pc-relative */
unsigned r_length:2; /* 0=byte, 1=word, 2=long, 3=24bits shifted by 2 */
unsigned r_extern:1; /* 1 if need to add symbol to value */
unsigned r_neg:1; /* 1 if addend is negative */
unsigned r_baserel:1; /* 1 if linkage table relative */
unsigned r_jmptable:1; /* 1 if relocation to jump table */
unsigned r_relative:1; /* 1 if load address relative */
};
#define relocation_info relocation_info_arm6
/* No special executable format */
#define cpu_exec_aout_makecmds(a, b) ENOEXEC
#endif /* _ARM_AOUT_MACHDEP_H_ */

34
sys/arch/arm/include/apmvar.h
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@ -1,34 +0,0 @@
/* $NetBSD: apmvar.h,v 1.2 2014/02/24 16:57:57 christos Exp $ */
/*-
* Copyright (c) 1995 The NetBSD Foundation, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_APMVAR_H_
#define _ARM_APMVAR_H_
#include <dev/apm/apmbios.h>
#include <dev/apm/apmio.h>
#endif /* _ARM_APMVAR_H_ */

7
sys/arch/arm/include/arm26/Makefile
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@ -1,7 +0,0 @@
# $NetBSD: Makefile,v 1.2 2002/11/26 23:30:12 lukem Exp $
INCSDIR= /usr/include/arm/arm26
INCS= types.h
.include <bsd.kinc.mk>

47
sys/arch/arm/include/arm26/types.h
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@ -1,47 +0,0 @@
/* $NetBSD: types.h,v 1.1 2001/11/22 17:59:57 thorpej Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_ARM26_TYPES_H_
#define _ARM_ARM26_TYPES_H_
#ifdef _KERNEL
#define __PROG26 /* indicate 26-bit mode */
#endif
#include <arm/types.h> /* pull in generic ARM definitions */
#endif /* _ARM_ARM26_TYPES_H_ */

7
sys/arch/arm/include/arm32/Makefile
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@ -1,7 +0,0 @@
# $NetBSD: Makefile,v 1.10 2014/10/25 10:58:12 skrll Exp $
INCSDIR= /usr/include/arm/arm32
INCS= frame.h param.h pmap.h psl.h pte.h rtc.h types.h vmparam.h
.include <bsd.kinc.mk>

17
sys/arch/arm/include/arm32/db_machdep.h
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@ -1,17 +0,0 @@
/* $NetBSD: db_machdep.h,v 1.9 2014/03/28 21:54:12 matt Exp $ */
#ifndef _ARM32_DB_MACHDEP_H_
#define _ARM32_DB_MACHDEP_H_
#include <arm/db_machdep.h>
void db_show_frame_cmd(db_expr_t, bool, db_expr_t, const char *);
void db_show_fault_cmd(db_expr_t, bool, db_expr_t, const char *);
#ifdef _KERNEL
void db_show_tlb_cmd(db_expr_t, bool, db_expr_t, const char *);
#endif
#if defined(_KERNEL) && defined(MULTIPROCESSOR)
void db_switch_cpu_cmd(db_expr_t, bool, db_expr_t, const char *);
#endif
#endif

478
sys/arch/arm/include/arm32/frame.h
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@ -1,478 +0,0 @@
/* $NetBSD: frame.h,v 1.42 2015/04/17 17:28:33 matt Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* frame.h
*
* Stack frames structures
*
* Created : 30/09/94
*/
#ifndef _ARM32_FRAME_H_
#define _ARM32_FRAME_H_
#include <arm/frame.h> /* Common ARM stack frames */
#ifndef _LOCORE
/*
* Switch frame.
*
* Should be a multiple of 8 bytes for dumpsys.
*/
struct switchframe {
u_int sf_r4;
u_int sf_r5;
u_int sf_r6;
u_int sf_r7;
u_int sf_sp;
u_int sf_pc;
};
/*
* System stack frames.
*/
struct clockframe {
struct trapframe cf_tf;
};
/*
* Stack frame. Used during stack traces (db_trace.c)
*/
struct frame {
u_int fr_fp;
u_int fr_sp;
u_int fr_lr;
u_int fr_pc;
};
#ifdef _KERNEL
void validate_trapframe(trapframe_t *, int);
#endif /* _KERNEL */
#else /* _LOCORE */
#include "opt_compat_netbsd.h"
#include "opt_execfmt.h"
#include "opt_multiprocessor.h"
#include "opt_cpuoptions.h"
#include "opt_arm_debug.h"
#include "opt_cputypes.h"
#include <arm/locore.h>
/*
* This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process
* any pending softints.
*/
#ifdef _ARM_ARCH_4T
#define B_CF_CONTROL(rX) ;\
ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\
bx ip /* branch to cpu_control */
#else
#define B_CF_CONTROL(rX) ;\
ldr pc, [rX, #CF_CONTROL] /* branch to cpu_control */
#endif
#ifdef _ARM_ARCH_5T
#define BL_CF_CONTROL(rX) ;\
ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\
blx ip /* call cpu_control */
#else
#define BL_CF_CONTROL(rX) ;\
mov lr, pc ;\
ldr pc, [rX, #CF_CONTROL] /* call cpu_control */
#endif
#if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
#define DO_PENDING_SOFTINTS \
ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\
cmp r0, #0 /* Test for 0. */ ;\
bne 10f /* skip softints if != 0 */ ;\
ldr r0, [r4, #CI_CPL] /* Get current priority level */;\
ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\
lsrs r0, r1, r0 /* shift mask by cpl */ ;\
blne _C_LABEL(dosoftints) /* dosoftints(void) */ ;\
10:
#else
#define DO_PENDING_SOFTINTS /* nothing */
#endif
#ifdef _ARM_ARCH_6
#define GET_CPSR(rb) /* nothing */
#define CPSID_I(ra,rb) cpsid i
#define CPSIE_I(ra,rb) cpsie i
#else
#define GET_CPSR(rb) \
mrs rb, cpsr /* fetch CPSR */
#define CPSID_I(ra,rb) \
orr ra, rb, #(IF32_bits) ;\
msr cpsr_c, ra /* Disable interrupts */
#define CPSIE_I(ra,rb) \
bic ra, rb, #(IF32_bits) ;\
msr cpsr_c, ra /* Restore interrupts */
#endif
#ifdef __HAVE_PREEMPTION
#define DO_CLEAR_ASTPENDING \
mvn r1, #1 /* complement of 1 */ ;\
add r0, r4, #CI_ASTPENDING /* address of astpending */ ;\
bl _C_LABEL(atomic_and_uint) /* clear AST */
#else
#define DO_CLEAR_ASTPENDING \
mov r0, #0 ;\
str r0, [r4, #CI_ASTPENDING] /* clear AST */
#endif
#define DO_PENDING_AST(lbl) ;\
1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\
tst r1, #0x00000001 ;\
beq lbl /* Nope. Just bail */ ;\
DO_CLEAR_ASTPENDING ;\
CPSIE_I(r5, r5) /* Restore interrupts */ ;\
mov r0, sp ;\
bl _C_LABEL(ast) /* ast(frame) */ ;\
CPSID_I(r0, r5) /* Disable interrupts */ ;\
b 1b /* test again */
/*
* AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS
* These are used in order to support dynamic enabling/disabling of
* alignment faults when executing old a.out ARM binaries.
*
* Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain
* pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
* relies on r4 being preserved.
*/
#ifdef EXEC_AOUT
#define AST_ALIGNMENT_FAULT_LOCALS \
.Laflt_cpufuncs: ;\
.word _C_LABEL(cpufuncs)
/*
* This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at
* the top of interrupt/exception handlers.
*
* When invoked, r0 *must* contain the value of SPSR on the current
* trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS
* is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME.
*/
#define ENABLE_ALIGNMENT_FAULTS \
and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\
cmp r7, #(PSR_USR32_MODE) ;\
GET_CURCPU(r4) /* r4 = cpuinfo */ ;\
bne 1f /* Not USR mode skip AFLT */ ;\
ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\
ldr r1, [r1, #L_MD_FLAGS] /* Fetch l_md.md_flags */ ;\
tst r1, #MDLWP_NOALIGNFLT ;\
beq 1f /* AFLTs already enabled */ ;\
ldr r2, .Laflt_cpufuncs ;\
ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\
mov r0, #-1 ;\
BL_CF_CONTROL(r2) /* Enable alignment faults */ ;\
1: /* done */
/*
* This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or
* PULLFRAME at the end of interrupt/exception handlers. We know that
* r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did
* for use.
*/
#define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \
DO_PENDING_SOFTINTS ;\
GET_CPSR(r5) /* save CPSR */ ;\
CPSID_I(r1, r5) /* Disable interrupts */ ;\
cmp r7, #(PSR_USR32_MODE) /* Returning to USR mode? */ ;\
bne 3f /* Nope, get out now */ ;\
DO_PENDING_AST(2f) /* Pending AST? */ ;\
2: ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\
ldr r0, [r1, #L_MD_FLAGS] /* get md_flags from lwp */ ;\
tst r0, #MDLWP_NOALIGNFLT ;\
beq 3f /* Keep AFLTs enabled */ ;\
ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\
ldr r2, .Laflt_cpufuncs ;\
mov r0, #-1 ;\
bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\
BL_CF_CONTROL(r2) /* Set new CTRL reg value */ ;\
3: /* done */
#else /* !EXEC_AOUT */
#define AST_ALIGNMENT_FAULT_LOCALS
#define ENABLE_ALIGNMENT_FAULTS \
and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\
GET_CURCPU(r4) /* r4 = cpuinfo */
#define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \
DO_PENDING_SOFTINTS ;\
GET_CPSR(r5) /* save CPSR */ ;\
CPSID_I(r1, r5) /* Disable interrupts */ ;\
cmp r7, #(PSR_USR32_MODE) ;\
bne 2f /* Nope, get out now */ ;\
DO_PENDING_AST(2f) /* Pending AST? */ ;\
2: /* done */
#endif /* EXEC_AOUT */
#ifndef _ARM_ARCH_6
#ifdef ARM_LOCK_CAS_DEBUG
#define LOCK_CAS_DEBUG_LOCALS \
.L_lock_cas_restart: ;\
.word _C_LABEL(_lock_cas_restart)
#if defined(__ARMEB__)
#define LOCK_CAS_DEBUG_COUNT_RESTART \
ble 99f ;\
ldr r0, .L_lock_cas_restart ;\
ldmia r0, {r1-r2} /* load ev_count */ ;\
adds r2, r2, #1 /* 64-bit incr (lo) */ ;\
adc r1, r1, #0 /* 64-bit incr (hi) */ ;\
stmia r0, {r1-r2} /* store ev_count */
#else /* __ARMEB__ */
#define LOCK_CAS_DEBUG_COUNT_RESTART \
ble 99f ;\
ldr r0, .L_lock_cas_restart ;\
ldmia r0, {r1-r2} /* load ev_count */ ;\
adds r1, r1, #1 /* 64-bit incr (lo) */ ;\
adc r2, r2, #0 /* 64-bit incr (hi) */ ;\
stmia r0, {r1-r2} /* store ev_count */
#endif /* __ARMEB__ */
#else /* ARM_LOCK_CAS_DEBUG */
#define LOCK_CAS_DEBUG_LOCALS /* nothing */
#define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */
#endif /* ARM_LOCK_CAS_DEBUG */
#define LOCK_CAS_CHECK_LOCALS \
.L_lock_cas: ;\
.word _C_LABEL(_lock_cas) ;\
.L_lock_cas_end: ;\
.word _C_LABEL(_lock_cas_end) ;\
LOCK_CAS_DEBUG_LOCALS
#define LOCK_CAS_CHECK \
ldr r0, [sp] /* get saved PSR */ ;\
and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\
cmp r0, #(PSR_SVC32_MODE) ;\
bne 99f /* nope, get out now */ ;\
ldr r0, [sp, #(TF_PC)] ;\
ldr r1, .L_lock_cas_end ;\
cmp r0, r1 ;\
bge 99f ;\
ldr r1, .L_lock_cas ;\
cmp r0, r1 ;\
strgt r1, [sp, #(TF_PC)] ;\
LOCK_CAS_DEBUG_COUNT_RESTART ;\
99:
#else
#define LOCK_CAS_CHECK /* nothing */
#define LOCK_CAS_CHECK_LOCALS /* nothing */
#endif
/*
* ASM macros for pushing and pulling trapframes from the stack
*
* These macros are used to handle the trapframe structure defined above.
*/
/*
* PUSHFRAME - macro to push a trap frame on the stack in the current mode
* Since the current mode is used, the SVC lr field is not defined.
*/
#ifdef CPU_SA110
/*
* NOTE: r13 and r14 are stored separately as a work around for the
* SA110 rev 2 STM^ bug
*/
#define PUSHUSERREGS \
stmia sp, {r0-r12}; /* Push the user mode registers */ \
add r0, sp, #(TF_USR_SP-TF_R0); /* Adjust the stack pointer */ \
stmia r0, {r13-r14}^ /* Push the user mode registers */
#else
#define PUSHUSERREGS \
stmia sp, {r0-r14}^ /* Push the user mode registers */
#endif
#define PUSHFRAME \
str lr, [sp, #-4]!; /* Push the return address */ \
sub sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \
PUSHUSERREGS; /* Push the user mode registers */ \
mov r0, r0; /* NOP for previous instruction */ \
mrs r0, spsr; /* Get the SPSR */ \
str r0, [sp, #-TF_R0]! /* Push the SPSR on the stack */
/*
* Push a minimal trapframe so we can dispatch an interrupt from the
* idle loop. The only reason the idle loop wakes up is to dispatch
* interrupts so why take the avoid of a full exception when we can do
* something minimal.
*/
#define PUSHIDLEFRAME \
str lr, [sp, #-4]!; /* save SVC32 lr */ \
str r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */ \
str r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */ \
mrs r0, cpsr; /* Get the CPSR */ \
str r0, [sp, #(-TF_R4)]! /* Push the CPSR on the stack */
/*
* Push a trapframe to be used by cpu_switchto
*/
#define PUSHSWITCHFRAME(rX) \
mov ip, sp; \
sub sp, sp, #(TRAPFRAMESIZE-TF_R12); /* Adjust the stack pointer */ \
push {r4-r11}; /* Push the callee saved registers */ \
sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \
str ip, [sp, #TF_SVC_SP]; \
str lr, [sp, #TF_SVC_LR]; \
str lr, [sp, #TF_PC]; \
mrs rX, cpsr; /* Get the CPSR */ \
str rX, [sp, #TF_SPSR] /* save in trapframe */
#define PUSHSWITCHFRAME1 \
mov ip, sp; \
sub sp, sp, #(TRAPFRAMESIZE-TF_R8); /* Adjust the stack pointer */ \
push {r4-r7}; /* Push some of the callee saved registers */ \
sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \
str ip, [sp, #TF_SVC_SP]; \
str lr, [sp, #TF_SVC_LR]; \
str lr, [sp, #TF_PC]
#if defined(_ARM_ARCH_DWORD_OK) && __ARM_EABI__
#define PUSHSWITCHFRAME2 \
strd r10, [sp, #TF_R10]; /* save r10 & r11 */ \
strd r8, [sp, #TF_R8]; /* save r8 & r9 */ \
mrs r0, cpsr; /* Get the CPSR */ \
str r0, [sp, #TF_SPSR] /* save in trapframe */
#else
#define PUSHSWITCHFRAME2 \
add r0, sp, #TF_R8; /* get ptr to r8 and above */ \
stmia r0, {r8-r11}; /* save rest of registers */ \
mrs r0, cpsr; /* Get the CPSR */ \
str r0, [sp, #TF_SPSR] /* save in trapframe */
#endif
/*
* PULLFRAME - macro to pull a trap frame from the stack in the current mode
* Since the current mode is used, the SVC lr field is ignored.
*/
#define PULLFRAME \
ldr r0, [sp], #TF_R0; /* Pop the SPSR from stack */ \
msr spsr_fsxc, r0; \
ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
mov r0, r0; /* NOP for previous instruction */ \
add sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \
ldr lr, [sp], #0x0004 /* Pop the return address */
#define PULLIDLEFRAME \
add sp, sp, #TF_R4; /* Adjust the stack pointer */ \
ldr r4, [sp], #(TF_R6-TF_R4); /* restore callee-saved r4 */ \
ldr r6, [sp], #(TF_PC-TF_R6); /* restore callee-saved r6 */ \
ldr lr, [sp], #4 /* Pop the return address */
/*
* Pop a trapframe to be used by cpu_switchto (don't touch r0 & r1).
*/
#define PULLSWITCHFRAME \
add sp, sp, #TF_R4; /* Adjust the stack pointer */ \
pop {r4-r11}; /* pop the callee saved registers */ \
add sp, sp, #(TF_PC-TF_R12); /* Adjust the stack pointer */ \
ldr lr, [sp], #4; /* pop the return address */
/*
* PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
* This should only be used if the processor is not currently in SVC32
* mode. The processor mode is switched to SVC mode and the trap frame is
* stored. The SVC lr field is used to store the previous value of
* lr in SVC mode.
*
* NOTE: r13 and r14 are stored separately as a work around for the
* SA110 rev 2 STM^ bug
*/
#ifdef _ARM_ARCH_6
#define SET_CPSR_MODE(tmp, mode) \
cps #(mode)
#else
#define SET_CPSR_MODE(tmp, mode) \
mrs tmp, cpsr; /* Get the CPSR */ \
bic tmp, tmp, #(PSR_MODE); /* Fix for SVC mode */ \
orr tmp, tmp, #(mode); \
msr cpsr_c, tmp /* Punch into SVC mode */
#endif
#define PUSHFRAMEINSVC \
stmdb sp, {r0-r3}; /* Save 4 registers */ \
mov r0, lr; /* Save xxx32 r14 */ \
mov r1, sp; /* Save xxx32 sp */ \
mrs r3, spsr; /* Save xxx32 spsr */ \
SET_CPSR_MODE(r2, PSR_SVC32_MODE); \
bic r2, sp, #7; /* Align new SVC sp */ \
str r0, [r2, #-4]!; /* Push return address */ \
stmdb r2!, {sp, lr}; /* Push SVC sp, lr */ \
mov sp, r2; /* Keep stack aligned */ \
msr spsr_fsxc, r3; /* Restore correct spsr */ \
ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
sub sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \
PUSHUSERREGS; /* Push the user mode registers */ \
mov r0, r0; /* NOP for previous instruction */ \
mrs r0, spsr; /* Get the SPSR */ \
str r0, [sp, #-TF_R0]! /* Push the SPSR onto the stack */
/*
* PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
* in SVC32 mode and restore the saved processor mode and PC.
* This should be used when the SVC lr register needs to be restored on
* exit.
*/
#define PULLFRAMEFROMSVCANDEXIT \
ldr r0, [sp], #0x0008; /* Pop the SPSR from stack */ \
msr spsr_fsxc, r0; /* restore SPSR */ \
ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
mov r0, r0; /* NOP for previous instruction */ \
add sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \
ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
#endif /* _LOCORE */
#endif /* _ARM32_FRAME_H_ */

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sys/arch/arm/include/arm32/machdep.h
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/* $NetBSD: machdep.h,v 1.18 2014/03/28 21:51:59 matt Exp $ */
#ifndef _ARM32_BOOT_MACHDEP_H_
#define _ARM32_BOOT_MACHDEP_H_
/* Define various stack sizes in pages */
#ifndef IRQ_STACK_SIZE
#define IRQ_STACK_SIZE 1
#endif
#ifndef ABT_STACK_SIZE
#define ABT_STACK_SIZE 1
#endif
#ifndef UND_STACK_SIZE
#ifdef IPKDB
#define UND_STACK_SIZE 2
#else
#define UND_STACK_SIZE 1
#endif
#endif
#ifndef FIQ_STACK_SIZE
#define FIQ_STACK_SIZE 1
#endif
extern void (*cpu_reset_address)(void);
extern paddr_t cpu_reset_address_paddr;
extern u_int data_abort_handler_address;
extern u_int prefetch_abort_handler_address;
// extern u_int undefined_handler_address;
#define undefined_handler_address (curcpu()->ci_undefsave[2])
struct bootmem_info {
paddr_t bmi_start;
paddr_t bmi_kernelstart;
paddr_t bmi_kernelend;
paddr_t bmi_end;
pv_addrqh_t bmi_freechunks;
pv_addrqh_t bmi_chunks; /* sorted list of memory to be mapped */
pv_addr_t bmi_freeblocks[4];
/*
* These need to be static for pmap's kernel_pt list.
*/
pv_addr_t bmi_vector_l2pt;
pv_addr_t bmi_io_l2pt;
pv_addr_t bmi_l2pts[32]; // for large memory disks.
u_int bmi_freepages;
u_int bmi_nfreeblocks;
};
extern struct bootmem_info bootmem_info;
extern char *booted_kernel;
extern volatile uint32_t arm_cpu_hatched;
extern volatile uint32_t arm_cpu_mbox;
extern u_int arm_cpu_max;
/* misc prototypes used by the many arm machdeps */
void cortex_pmc_ccnt_init(void);
void cpu_hatch(struct cpu_info *, cpuid_t, void (*)(struct cpu_info *));
void halt(void);
void parse_mi_bootargs(char *);
void data_abort_handler(trapframe_t *);
void prefetch_abort_handler(trapframe_t *);
void undefinedinstruction_bounce(trapframe_t *);
void dumpsys(void);
/*
* note that we use void *as all the platforms have different ideas on what
* the structure is
*/
u_int initarm(void *);
struct pmap_devmap;
struct boot_physmem;
void arm32_bootmem_init(paddr_t memstart, psize_t memsize, paddr_t kernelstart);
void arm32_kernel_vm_init(vaddr_t kvm_base, vaddr_t vectors,
vaddr_t iovbase /* (can be zero) */,
const struct pmap_devmap *devmap, bool mapallmem_p);
vaddr_t initarm_common(vaddr_t kvm_base, vsize_t kvm_size,
const struct boot_physmem *bp, size_t nbp);
/* from arm/arm32/intr.c */
void dosoftints(void);
void set_spl_masks(void);
#ifdef DIAGNOSTIC
void dump_spl_masks(void);
#endif
#endif

115
sys/arch/arm/include/arm32/param.h
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@ -1,115 +0,0 @@
/* $NetBSD: param.h,v 1.24 2015/04/02 03:11:01 matt Exp $ */
/*
* Copyright (c) 1994,1995 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the RiscBSD team.
* 4. The name "RiscBSD" nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ARM_ARM32_PARAM_H_
#define _ARM_ARM32_PARAM_H_
#ifdef _KERNEL_OPT
# include "opt_arm32_pmap.h"
#endif
/*
* Machine dependent constants for ARM6+ processors
*/
/* These are defined in the Port File before it includes
* this file. */
#if defined(__minix)
/* We do not support PAGE_SIZE != 4k */
#define PGSHIFT 12 /* LOG2(NBPG) */
#endif /* defined(__minix) */
#ifndef PGSHIFT
#if defined(_ARM_ARCH_6)
#define PGSHIFT 13 /* LOG2(NBPG) */
#else
#define PGSHIFT 12 /* LOG2(NBPG) */
#endif
#endif
#define NBPG (1 << PGSHIFT) /* bytes/page */
#define PGOFSET (NBPG-1) /* byte offset into page */
#define NPTEPG (NBPG/(sizeof (pt_entry_t)))
#define SSIZE 1 /* initial stack size/NBPG */
#define SINCR 1 /* increment of stack/NBPG */
#define USPACE 8192 /* total size of u-area */
#define UPAGES (USPACE / NBPG) /* pages of u-area */
#ifndef MSGBUFSIZE
#define MSGBUFSIZE 16384 /* default message buffer size */
#endif
/*
* Minimum and maximum sizes of the kernel malloc arena in PAGE_SIZE-sized
* logical pages.
*/
#define NKMEMPAGES_MIN_DEFAULT ((8 * 1024 * 1024) >> PAGE_SHIFT)
#define NKMEMPAGES_MAX_DEFAULT ((128 * 1024 * 1024) >> PAGE_SHIFT)
/* Constants used to divide the USPACE area */
/*
* The USPACE area contains :
* 1. the pcb structure for the process
* 2. the kernel (svc) stack
*
* The layout of the area looks like this
*
* | uarea | kernel stack |
*
* The size of the uarea is known.
* The kernel stack should be at least 4K is size.
*
* The stack top addresses are used to set the stack pointers. The stack bottom
* addresses at the addresses monitored by the diagnostic code for stack overflows
*
*/
#define USPACE_SVC_STACK_TOP (USPACE)
#define USPACE_SVC_STACK_BOTTOM (sizeof(struct pcb))
#define arm_btop(x) ((unsigned)(x) >> PGSHIFT)
#define arm_ptob(x) ((unsigned)(x) << PGSHIFT)
#define arm_trunc_page(x) ((unsigned)(x) & ~PGOFSET)
#ifdef _KERNEL
#ifndef _LOCORE
void delay(unsigned);
#define DELAY(x) delay(x)
#endif
#endif
#include <arm/param.h>
#endif /* _ARM_ARM32_PARAM_H_ */

1111
sys/arch/arm/include/arm32/pmap.h
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95
sys/arch/arm/include/arm32/psl.h
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/* $NetBSD: psl.h,v 1.20 2014/02/04 18:51:16 matt Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* psl.h
*
* spl prototypes.
* Eventually this will become a set of defines.
*
* Created : 21/07/95
*/
#ifndef _ARM_PSL_H_
#define _ARM_PSL_H_
#include <machine/intr.h>
/*
* These are the different SPL states
*
* Each state has an interrupt mask associated with it which
* indicate which interrupts are allowed.
*/
#define spl0() splx(IPL_NONE)
#define splsoftclock() raisespl(IPL_SOFTCLOCK)
#define splsoftbio() raisespl(IPL_SOFTBIO)
#define splsoftnet() raisespl(IPL_SOFTNET)
#define splsoftserial() raisespl(IPL_SOFTSERIAL)
#define splvm() raisespl(IPL_VM)
#define splsched() raisespl(IPL_SCHED)
#define splhigh() raisespl(IPL_HIGH)
#define IPL_SAFEPRI IPL_NONE /* for kern_sleepq.c */
#ifdef _KERNEL
#ifndef _LOCORE
int raisespl (int);
int lowerspl (int);
void splx (int);
typedef uint8_t ipl_t;
typedef struct {
uint8_t _ipl;
} ipl_cookie_t;
static inline ipl_cookie_t
makeiplcookie(ipl_t ipl)
{
return (ipl_cookie_t){._ipl = (uint8_t)ipl};
}
static inline int
splraiseipl(ipl_cookie_t icookie)
{
return raisespl(icookie._ipl);
}
#endif /* _LOCORE */
#endif /* _KERNEL */
#endif /* _ARM_PSL_H_ */
/* End of psl.h */

337
sys/arch/arm/include/arm32/pte.h
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/* $NetBSD: pte.h,v 1.19 2014/10/29 10:59:48 skrll Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_PTE_H_
#define _ARM_PTE_H_
/*
* The ARM MMU architecture was introduced with ARM v3 (previous ARM
* architecture versions used an optional off-CPU memory controller
* to perform address translation).
*
* The ARM MMU consists of a TLB and translation table walking logic.
* There is typically one TLB per memory interface (or, put another
* way, one TLB per software-visible cache).
*
* The ARM MMU is capable of mapping memory in the following chunks:
*
* 16M SuperSections (L1 table, ARMv6+)
*
* 1M Sections (L1 table)
*
* 64K Large Pages (L2 table)
*
* 4K Small Pages (L2 table)
*
* 1K Tiny Pages (L2 table)
*
* There are two types of L2 tables: Coarse Tables and Fine Tables (not
* available on ARMv6+). Coarse Tables can map Large and Small Pages.
* Fine Tables can map Tiny Pages.
*
* Coarse Tables can define 4 Subpages within Large and Small pages.
* Subpages define different permissions for each Subpage within
* a Page. ARMv6 format Coarse Tables have no subpages.
*
* Coarse Tables are 1K in length. Fine tables are 4K in length.
*
* The Translation Table Base register holds the pointer to the
* L1 Table. The L1 Table is a 16K contiguous chunk of memory
* aligned to a 16K boundary. Each entry in the L1 Table maps
* 1M of virtual address space, either via a Section mapping or
* via an L2 Table.
*
* ARMv6+ has a second TTBR register which can be used if any of the
* upper address bits are non-zero (think kernel). For NetBSD, this
* would be 1 upper bit splitting user/kernel in a 2GB/2GB split.
* This would also reduce the size of the L1 Table to 8K.
*
* In addition, the Fast Context Switching Extension (FCSE) is available
* on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating
* TLB/cache flushes on context switch by use of a smaller address space
* and a "process ID" that modifies the virtual address before being
* presented to the translation logic.
*/
#ifndef _LOCORE
typedef uint32_t pd_entry_t; /* L1 table entry */
typedef uint32_t pt_entry_t; /* L2 table entry */
#endif /* _LOCORE */
#define L1_SS_SIZE 0x01000000 /* 16M */
#define L1_SS_OFFSET (L1_SS_SIZE - 1)
#define L1_SS_FRAME (~L1_SS_OFFSET)
#define L1_SS_SHIFT 24
#define L1_S_SIZE 0x00100000 /* 1M */
#define L1_S_OFFSET (L1_S_SIZE - 1)
#define L1_S_FRAME (~L1_S_OFFSET)
#define L1_S_SHIFT 20
#define L2_L_SIZE 0x00010000 /* 64K */
#define L2_L_OFFSET (L2_L_SIZE - 1)
#define L2_L_FRAME (~L2_L_OFFSET)
#define L2_L_SHIFT 16
#define L2_S_SEGSIZE (PAGE_SIZE * L2_S_SIZE / 4)
#define L2_S_SIZE 0x00001000 /* 4K */
#define L2_S_OFFSET (L2_S_SIZE - 1)
#define L2_S_FRAME (~L2_S_OFFSET)
#define L2_S_SHIFT 12
#define L2_T_SIZE 0x00000400 /* 1K */
#define L2_T_OFFSET (L2_T_SIZE - 1)
#define L2_T_FRAME (~L2_T_OFFSET)
#define L2_T_SHIFT 10
/*
* The NetBSD VM implementation only works on whole pages (4K),
* whereas the ARM MMU's Coarse tables are sized in terms of 1K
* (16K L1 table, 1K L2 table).
*
* So, we allocate L2 tables 4 at a time, thus yielding a 4K L2
* table.
*/
#define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */
#define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */
#define L1_TABLE_SIZE 0x4000 /* 16K */
#define L2_TABLE_SIZE 0x1000 /* 4K */
/*
* The new pmap deals with the 1KB coarse L2 tables by
* allocating them from a pool. Until every port has been converted,
* keep the old L2_TABLE_SIZE define lying around. Converted ports
* should use L2_TABLE_SIZE_REAL until then.
*/
#define L1_TABLE_SIZE_REAL 0x4000 /* 16K */
#define L2_TABLE_SIZE_REAL 0x400 /* 1K */
/*
* ARM L1 Descriptors
*/
#define L1_TYPE_INV 0x00 /* Invalid (fault) */
#define L1_TYPE_C 0x01 /* Coarse L2 */
#define L1_TYPE_S 0x02 /* Section */
#define L1_TYPE_F 0x03 /* Fine L2 */
#define L1_TYPE_MASK 0x03 /* mask of type bits */
/* L1 Section Descriptor */
#define L1_S_B 0x00000004 /* bufferable Section */
#define L1_S_C 0x00000008 /* cacheable Section */
#define L1_S_IMP 0x00000010 /* implementation defined */
#define L1_S_DOM(x) ((x) << 5) /* domain */
#define L1_S_DOM_MASK L1_S_DOM(0xf)
#define L1_S_AP(x) ((x) << 10) /* access permissions */
#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */
#define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */
#define L1_S_XS_TEX(x) ((x) << 12) /* Type Extension */
#define L1_S_V6_TEX(x) L1_S_XS_TEX(x)
#define L1_S_V6_P 0x00000200 /* ECC enable for this section */
#define L1_S_V6_SUPER 0x00040000 /* ARMv6 SuperSection (16MB) bit */
#define L1_S_V6_XN L1_S_IMP /* ARMv6 eXecute Never */
#define L1_S_V6_APX 0x00008000 /* ARMv6 AP eXtension */
#define L1_S_V6_S 0x00010000 /* ARMv6 Shared */
#define L1_S_V6_nG 0x00020000 /* ARMv6 not-Global */
#define L1_S_V6_SS 0x00040000 /* ARMv6 SuperSection */
#define L1_S_V6_NS 0x00080000 /* ARMv6 Not Secure */
/* L1 Coarse Descriptor */
#define L1_C_IMP0 0x00000004 /* implementation defined */
#define L1_C_IMP1 0x00000008 /* implementation defined */
#define L1_C_IMP2 0x00000010 /* implementation defined */
#define L1_C_DOM(x) ((x) << 5) /* domain */
#define L1_C_DOM_MASK L1_C_DOM(0xf)
#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */
#define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */
#define L1_C_V6_P 0x00000200 /* ECC enable for this section */
/* L1 Fine Descriptor */
#define L1_F_IMP0 0x00000004 /* implementation defined */
#define L1_F_IMP1 0x00000008 /* implementation defined */
#define L1_F_IMP2 0x00000010 /* implementation defined */
#define L1_F_DOM(x) ((x) << 5) /* domain */
#define L1_F_DOM_MASK L1_F_DOM(0xf)
#define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */
#define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */
/*
* ARM L2 Descriptors
*/
#define L2_TYPE_INV 0x00 /* Invalid (fault) */
#define L2_TYPE_L 0x01 /* Large Page */
#define L2_TYPE_S 0x02 /* Small Page */
#define L2_TYPE_T 0x03 /* Tiny Page (not armv7) */
#define L2_TYPE_MASK 0x03 /* mask of type bits */
/*
* This L2 Descriptor type is available on XScale processors
* when using a Coarse L1 Descriptor. The Extended Small
* Descriptor has the same format as the XScale Tiny Descriptor,
* but describes a 4K page, rather than a 1K page.
* For V6 MMU, this is used when XP bit is cleared.
*/
#define L2_TYPE_XS 0x03 /* XScale/ARMv6 Extended Small Page */
#define L2_B 0x00000004 /* Bufferable page */
#define L2_C 0x00000008 /* Cacheable page */
#define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */
#define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */
#define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */
#define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */
#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
#define L2_XS_L_TEX(x) ((x) << 12) /* Type Extension */
#define L2_XS_T_TEX(x) ((x) << 6) /* Type Extension */
#define L2_XS_XN 0x00000001 /* ARMv6 eXecute Never (when XP=1) */
#define L2_XS_APX 0x00000200 /* ARMv6 AP eXtension */
#define L2_XS_S 0x00000400 /* ARMv6 Shared */
#define L2_XS_nG 0x00000800 /* ARMv6 Not-Global */
#define L2_V6_L_TEX L2_XS_L_TEX
#define L2_V6_XS_TEX L2_XS_T_TEX
#define L2_XS_L_XN 0x00008000 /* ARMv6 eXecute Never */
/*
* Access Permissions for L1 and L2 Descriptors.
*/
#define AP_W 0x01 /* writable */
#define AP_U 0x02 /* user */
/*
* Access Permissions for L1 and L2 of ARMv6 with XP=1 and ARMv7
*/
#define AP_R 0x01 /* readable */
#define AP_RO 0x20 /* read-only (L2_XS_APX >> 4) */
/*
* Short-hand for common AP_* constants.
*
* Note: These values assume the S (System) bit is set and
* the R (ROM) bit is clear in CP15 register 1.
*/
#define AP_KR 0x00 /* kernel read */
#define AP_KRW 0x01 /* kernel read/write */
#define AP_KRWUR 0x02 /* kernel read/write user read */
#define AP_KRWURW 0x03 /* kernel read/write user read/write */
/*
* Note: These values assume the S (System) and the R (ROM) bits are clear and
* the XP (eXtended page table) bit is set in CP15 register 1. ARMv6 only.
*/
#define APX_KR(APX) (APX|0x01) /* kernel read */
#define APX_KRUR(APX) (APX|0x02) /* kernel read user read */
#define APX_KRW(APX) ( 0x01) /* kernel read/write */
#define APX_KRWUR(APX) ( 0x02) /* kernel read/write user read */
#define APX_KRWURW(APX) ( 0x03) /* kernel read/write user read/write */
/*
* Note: These values are for the simplified access permissions model
* of ARMv7. Assumes that AFE is clear in CP15 register 1.
* Also used for ARMv6 with XP bit set.
*/
#define AP7_KR 0x21 /* kernel read */
#define AP7_KRUR 0x23 /* kernel read user read */
#define AP7_KRW 0x01 /* kernel read/write */
#define AP7_KRWURW 0x03 /* kernel read/write user read/write */
/*
* Domain Types for the Domain Access Control Register.
*/
#define DOMAIN_FAULT 0x00 /* no access */
#define DOMAIN_CLIENT 0x01 /* client */
#define DOMAIN_RESERVED 0x02 /* reserved */
#define DOMAIN_MANAGER 0x03 /* manager */
/*
* Type Extension bits for XScale processors.
*
* Behavior of C and B when X == 0:
*
* C B Cacheable Bufferable Write Policy Line Allocate Policy
* 0 0 N N - -
* 0 1 N Y - -
* 1 0 Y Y Write-through Read Allocate
* 1 1 Y Y Write-back Read Allocate
*
* Behavior of C and B when X == 1:
* C B Cacheable Bufferable Write Policy Line Allocate Policy
* 0 0 - - - - DO NOT USE
* 0 1 N Y - -
* 1 0 Mini-Data - - -
* 1 1 Y Y Write-back R/W Allocate
*/
#define TEX_XSCALE_X 0x01 /* X modifies C and B */
/*
* Type Extension bits for ARM V6 and V7 MMU
*
* TEX C B Shared
* 000 0 0 Strong order yes
* 000 0 1 Shared device yes
* 000 1 0 Outer and Inner write through, no write alloc S-bit
* 000 1 1 Outer and Inner write back, no write alloc S-bit
* 001 0 0 Outer and Inner non-cacheable S-bit
* 001 0 1 reserved
* 001 1 0 reserved
* 001 1 1 Outer and Inner write back, write alloc S-bit
* 010 0 0 Non-shared device no
* 010 0 1 reserved
* 010 1 X reserved
* 011 X X reserved
* 1BB A A BB for inner, AA for outer S-bit
*
* BB inner cache
* 0 0 Non-cacheable
* 0 1 Write back, write alloc
* 1 0 Write through, no write alloc
* 1 1 Write back, no write alloc
*
* AA outer cache
* 0 0 Non-cacheable
* 0 1 Write back, write alloc
* 1 0 Write through, no write alloc
* 1 1 Write back, no write alloc
*/
#define TEX_ARMV6_TEX 0x07 /* 3 bits in TEX */
#endif /* _ARM_PTE_H_ */

83
sys/arch/arm/include/arm32/rtc.h
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@ -1,83 +0,0 @@
/* $NetBSD: rtc.h,v 1.2 2009/03/14 14:45:55 dsl Exp $ */
/*
* Copyright (c) 1994 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* rtc.h
*
* Header file for RTC / CMOS stuff
*
* Created : 13/10/94
* Updated : 15/07/2000
*
* Based of kate/display/iiccontrol.c
*/
/*
* IIC addresses for RTC chip
* Two PCF8583 chips are supported on the IIC bus
*/
#define IIC_PCF8583_MASK 0xfc
#define IIC_PCF8583_ADDR 0xa0
#define RTC_Write (IIC_PCF8583_ADDR | IIC_WRITE)
#define RTC_Read (IIC_PCF8583_ADDR | IIC_READ)
typedef struct {
u_char rtc_micro;
u_char rtc_centi;
u_char rtc_sec;
u_char rtc_min;
u_char rtc_hour;
u_char rtc_day;
u_char rtc_mon;
u_char rtc_year;
u_char rtc_cen;
} rtc_t;
#define RTC_ADDR_CHECKSUM 0x3f
#define RTC_ADDR_BOOTOPTS 0x90
#define RTC_ADDR_REBOOTCNT 0x91
#define RTC_ADDR_YEAR 0xc0
#define RTC_ADDR_CENT 0xc1
#ifdef _KERNEL
int cmos_read(int);
int cmos_write(int, int);
#endif /* _KERNEL */
/* End of rtc.h */

53
sys/arch/arm/include/arm32/types.h
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@ -1,53 +0,0 @@
/* $NetBSD: types.h,v 1.11 2013/05/07 23:01:55 matt Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_ARM32_TYPES_H_
#define _ARM_ARM32_TYPES_H_
#ifdef _KERNEL
#define __PROG32 /* indicate 32-bit mode */
#ifdef _KERNEL_OPT
#include "opt_arm32_pmap.h"
#endif
#endif
#include <arm/types.h> /* pull in generic ARM definitions */
#define __HAVE_CPU_LWP_SETPRIVATE
#endif /* _ARM_ARM32_TYPES_H_ */

116
sys/arch/arm/include/arm32/vmparam.h
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@ -1,116 +0,0 @@
/* $NetBSD: vmparam.h,v 1.39 2015/06/20 07:13:25 skrll Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_ARM32_VMPARAM_H_
#define _ARM_ARM32_VMPARAM_H_
#if defined(_KERNEL) || defined(_KMEMUSER) || defined(__minix)
/*
* Virtual Memory parameters common to all arm32 platforms.
*/
#include <arm/cpuconf.h>
#include <arm/arm32/pte.h> /* pt_entry_t */
#define __USE_TOPDOWN_VM
#define USRSTACK VM_MAXUSER_ADDRESS
/*
* ARMv4 systems are normaly configured for 256MB KVA only, so restrict
* the size of the pager map to 4MB.
*/
#ifndef _ARM_ARCH_5
#define PAGER_MAP_DEFAULT_SIZE (4 * 1024 * 1024)
#endif
/*
* Note that MAXTSIZ can't be larger than 32M, otherwise the compiler
* would have to be changed to not generate "bl" instructions.
*/
#define MAXTSIZ (128*1024*1024) /* max text size */
#ifndef DFLDSIZ
#define DFLDSIZ (384*1024*1024) /* initial data size limit */
#endif
#ifndef MAXDSIZ
#define MAXDSIZ (1536*1024*1024) /* max data size */
#endif
#ifndef DFLSSIZ
#define DFLSSIZ (4*1024*1024) /* initial stack size limit */
#endif
#ifndef MAXSSIZ
#define MAXSSIZ (64*1024*1024) /* max stack size */
#endif
/*
* While the ARM architecture defines Section mappings, large pages,
* and small pages, the standard page size is (and will always be) 4K.
*/
#define PAGE_SHIFT PGSHIFT
#define PAGE_SIZE (1 << PAGE_SHIFT)
#define PAGE_MASK (PAGE_SIZE - 1)
/*
* Mach derived constants
*/
#define VM_MIN_ADDRESS ((vaddr_t) PAGE_SIZE)
#ifdef ARM_MMU_EXTENDED
#define VM_MAXUSER_ADDRESS ((vaddr_t) 0x80000000 - PAGE_SIZE)
#else
#define VM_MAXUSER_ADDRESS ((vaddr_t) KERNEL_BASE - PAGE_SIZE)
#endif
#define VM_MAX_ADDRESS VM_MAXUSER_ADDRESS
#define VM_MIN_KERNEL_ADDRESS ((vaddr_t) KERNEL_BASE)
#define VM_MAX_KERNEL_ADDRESS ((vaddr_t) -(PAGE_SIZE+1))
#if !defined(__minix)
#ifndef __ASSEMBLER__
/* XXX max. amount of KVM to be used by buffers. */
#ifndef VM_MAX_KERNEL_BUF
extern vaddr_t virtual_avail;
extern vaddr_t virtual_end;
#define VM_MAX_KERNEL_BUF \
((virtual_end - virtual_avail) * 4 / 10)
#endif
#endif /* __ASSEMBLER__ */
#endif /* !defined(__minix) */
#endif /* _KERNEL || _KMEMUSER */
#endif /* _ARM_ARM32_VMPARAM_H_ */

1074
sys/arch/arm/include/armreg.h
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236
sys/arch/arm/include/asm.h
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@ -1,236 +0,0 @@
/* $NetBSD: asm.h,v 1.27 2014/03/04 15:27:58 matt Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)asm.h 5.5 (Berkeley) 5/7/91
*/
#ifndef _ARM_ASM_H_
#define _ARM_ASM_H_
#include <arm/cdefs.h>
.syntax unified
#ifdef __thumb__
#define THUMB_INSN(n) n
#else
#define THUMB_INSN(n)
#endif
#define __BIT(n) (1 << (n))
#define __BITS(hi,lo) ((~((~0)<<((hi)+1)))&((~0)<<(lo)))
#define _C_LABEL(x) x
#define _ASM_LABEL(x) x
#ifdef __STDC__
# define __CONCAT(x,y) x ## y
# define __STRING(x) #x
#else
# define __CONCAT(x,y) x/**/y
# define __STRING(x) "x"
#endif
#ifndef _ALIGN_TEXT
# define _ALIGN_TEXT .align 2
#endif
#ifndef _TEXT_SECTION
#define _TEXT_SECTION .text
#endif
/*
* gas/arm uses @ as a single comment character and thus cannot be used here
* Instead it recognised the # instead of an @ symbols in .type directives
* We define a couple of macros so that assembly code will not be dependent
* on one or the other.
*/
#define _ASM_TYPE_FUNCTION %function
#define _ASM_TYPE_OBJECT %object
#define _THUMB_ENTRY(x) \
_TEXT_SECTION; _ALIGN_TEXT; .globl x; .type x,_ASM_TYPE_FUNCTION; \
.thumb_func; .code 16; x:
#define _ARM_ENTRY(x) \
_TEXT_SECTION; _ALIGN_TEXT; .globl x; .type x,_ASM_TYPE_FUNCTION; \
.code 32; x:
#ifdef __thumb__
#define _ENTRY(x) _THUMB_ENTRY(x)
#else
#define _ENTRY(x) _ARM_ENTRY(x)
#endif
#define _END(x) .size x,.-x
#ifdef GPROF
# define _PROF_PROLOGUE \
mov ip, lr; bl __mcount
#else
# define _PROF_PROLOGUE
#endif
#define ENTRY(y) _ENTRY(_C_LABEL(y)); _PROF_PROLOGUE
#define ENTRY_NP(y) _ENTRY(_C_LABEL(y))
#define END(y) _END(_C_LABEL(y))
#define ARM_ENTRY(y) _ARM_ENTRY(_C_LABEL(y)); _PROF_PROLOGUE
#define ARM_ENTRY_NP(y) _ARM_ENTRY(_C_LABEL(y))
#define THUMB_ENTRY(y) _THUMB_ENTRY(_C_LABEL(y)); _PROF_PROLOGUE
#define THUMB_ENTRY_NP(y) _THUMB_ENTRY(_C_LABEL(y))
#define ASENTRY(y) _ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE
#define ASENTRY_NP(y) _ENTRY(_ASM_LABEL(y))
#define ASEND(y) _END(_ASM_LABEL(y))
#define ARM_ASENTRY(y) _ARM_ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE
#define ARM_ASENTRY_NP(y) _ARM_ENTRY(_ASM_LABEL(y))
#define THUMB_ASENTRY(y) _THUMB_ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE
#define THUMB_ASENTRY_NP(y) _THUMB_ENTRY(_ASM_LABEL(y))
#define ASMSTR .asciz
#ifdef __PIC__
#define REL_SYM(a, b) ((a) - (b))
#define PLT_SYM(x) x
#define GOT_SYM(x) PIC_SYM(x, GOT)
#define GOT_GET(x,got,sym) \
ldr x, sym; \
ldr x, [x, got]
#define GOT_INIT(got,gotsym,pclabel) \
ldr got, gotsym; \
pclabel: add got, got, pc
#ifdef __thumb__
#define GOT_INITSYM(gotsym,pclabel) \
.align 0; \
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (pclabel+4)
#else
#define GOT_INITSYM(gotsym,pclabel) \
.align 0; \
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (pclabel+8)
#endif
#ifdef __STDC__
#define PIC_SYM(x,y) x ## ( ## y ## )
#else
#define PIC_SYM(x,y) x/**/(/**/y/**/)
#endif
#else
#define REL_SYM(a, b) (a)
#define PLT_SYM(x) x
#define GOT_SYM(x) x
#define GOT_GET(x,got,sym) \
ldr x, sym;
#define GOT_INIT(got,gotsym,pclabel)
#define GOT_INITSYM(gotsym,pclabel)
#define PIC_SYM(x,y) x
#endif /* __PIC__ */
#define RCSID(x) .pushsection ".ident"; .asciz x; .popsection
#define WEAK_ALIAS(alias,sym) \
.weak alias; \
alias = sym
/*
* STRONG_ALIAS: create a strong alias.
*/
#define STRONG_ALIAS(alias,sym) \
.globl alias; \
alias = sym
#ifdef __STDC__
#define WARN_REFERENCES(sym,msg) \
.pushsection .gnu.warning. ## sym; \
.ascii msg; \
.popsection
#else
#define WARN_REFERENCES(sym,msg) \
.pushsection .gnu.warning./**/sym; \
.ascii msg; \
.popsection
#endif /* __STDC__ */
#ifdef __thumb__
# define XPUSH push
# define XPOP pop
# define XPOPRET pop {pc}
#else
# define XPUSH stmfd sp!,
# define XPOP ldmfd sp!,
# ifdef _ARM_ARCH_5
# define XPOPRET ldmfd sp!, {pc}
# else
# define XPOPRET ldmfd sp!, {lr}; mov pc, lr
# endif
#endif
#if defined (_ARM_ARCH_4T)
# define RET bx lr
# define RETr(r) bx r
# if defined(__thumb__)
# if defined(_ARM_ARCH_7)
# define RETc(c) it c; __CONCAT(bx,c) lr
# endif
# else
# define RETc(c) __CONCAT(bx,c) lr
# endif
#else
# define RET mov pc, lr
# define RETr(r) mov pc, r
# define RETc(c) __CONCAT(mov,c) pc, lr
#endif
#ifdef _ARM_ARCH_7
#define KMODTRAMPOLINE(n) \
_ENTRY(__wrap_ ## n) \
movw ip, #:lower16:n; \
movt ip, #:upper16:n; \
bx ip
#elif defined(_ARM_ARCH_4T)
#define KMODTRAMPOLINE(n) \
_ENTRY(__wrap_ ## n) \
ldr ip, [pc]; \
bx ip; \
.word n
#else
#define KMODTRAMPOLINE(n) \
_ENTRY(__wrap_ ## n) \
ldr pc, [pc, #-4]; \
.word n
#endif
#if defined(__minix)
#define IMPORT(sym) \
.extern _C_LABEL(sym)
#define _LABEL(x) \
.globl x; x:
#define LABEL(y) _LABEL(_C_LABEL(y))
#endif /* defined(__minix) */
#endif /* !_ARM_ASM_H_ */

35
sys/arch/arm/include/atomic.h
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@ -1,35 +0,0 @@
/* $NetBSD: atomic.h,v 1.11 2008/11/19 06:39:17 matt Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas <matt@3am-software.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_ATOMIC_H_
#define _ARM_ATOMIC_H_
#endif /* _ARM_ATOMIC_H_ */

53
sys/arch/arm/include/blockio.h
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@ -1,53 +0,0 @@
/* $NetBSD: blockio.h,v 1.2 2001/06/02 10:44:56 bjh21 Exp $ */
/*-
* Copyright (c) 2001 Ben Harris
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* blockio.h - low level functions for bulk PIO data transfer
*/
#ifndef _ARM_BLOCKIO_H_
#define _ARM_BLOCKIO_H_
/*
* All these take three arguments:
* I/O address
* Memory address
* Number of bytes to copy
*/
void read_multi_1(u_int, void *, u_int);
void write_multi_1(u_int, const void *, u_int);
#define read_multi_2 insw16
#define write_multi_2 outsw16
void insw(u_int, void *, u_int);
void outsw(u_int, void *, u_int);
void insw16(u_int, void *, u_int);
void outsw16(u_int, void *, u_int);
#endif

59
sys/arch/arm/include/bootconfig.h
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@ -1,59 +0,0 @@
/* $NetBSD: bootconfig.h,v 1.7 2015/01/06 00:43:21 jmcneill Exp $ */
/*
* Copyright (c) 1994 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifdef _KERNEL
#define BOOTOPT_TYPE_BOOLEAN 0
#define BOOTOPT_TYPE_STRING 1
#define BOOTOPT_TYPE_INT 2
#define BOOTOPT_TYPE_BININT 3
#define BOOTOPT_TYPE_HEXINT 4
#define BOOTOPT_TYPE_MACADDR 5
#define BOOTOPT_TYPE_MASK 7
struct boot_physmem {
paddr_t bp_start; /* starting PFN (not address) */
psize_t bp_pages; /* # of pages */
u_int bp_freelist; /* VM_FREELIST_ * */
u_int bp_flags;
#define BOOT_PHYSMEM_CAN_DMA 1 /* Can DMA direct to this memory. */
};
int get_bootconf_option(char *, const char *, int, void *);
extern char *boot_args;
#endif /* _KERNEL */

15
sys/arch/arm/include/bswap.h
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@ -1,15 +0,0 @@
/* $NetBSD: bswap.h,v 1.6 2014/01/29 01:36:43 matt Exp $ */
#ifndef _ARM_BSWAP_H_
#define _ARM_BSWAP_H_
#ifdef __aarch64__
#include <aarch64/byte_swap.h>
#else
#include <arm/byte_swap.h>
#endif
#define __BSWAP_RENAME
#include <sys/bswap.h>
#endif /* !_ARM_BSWAP_H_ */

503
sys/arch/arm/include/bus_defs.h
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@ -1,503 +0,0 @@
/* $NetBSD: bus_defs.h,v 1.10 2014/01/29 00:42:15 matt Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_BUS_DEFS_H_
#define _ARM_BUS_DEFS_H_
#if defined(_KERNEL_OPT)
#include "opt_arm_bus_space.h"
#endif
/*
* Addresses (in bus space).
*/
typedef u_long bus_addr_t;
typedef u_long bus_size_t;
#define PRIxBUSADDR "lx"
#define PRIxBUSSIZE "lx"
#define PRIuBUSSIZE "lu"
/*
* Access methods for bus space.
*/
typedef struct bus_space *bus_space_tag_t;
typedef u_long bus_space_handle_t;
#define PRIxBSH "lx"
/*
* int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
* bus_size_t size, int flags, bus_space_handle_t *bshp);
*
* Map a region of bus space.
*/
#define BUS_SPACE_MAP_CACHEABLE 0x01
#define BUS_SPACE_MAP_LINEAR 0x02
#define BUS_SPACE_MAP_PREFETCHABLE 0x04
struct bus_space {
/* cookie */
void *bs_cookie;
/* mapping/unmapping */
int (*bs_map)(void *, bus_addr_t, bus_size_t,
int, bus_space_handle_t *);
void (*bs_unmap)(void *, bus_space_handle_t,
bus_size_t);
int (*bs_subregion)(void *, bus_space_handle_t,
bus_size_t, bus_size_t, bus_space_handle_t *);
/* allocation/deallocation */
int (*bs_alloc)(void *, bus_addr_t, bus_addr_t,
bus_size_t, bus_size_t, bus_size_t, int,
bus_addr_t *, bus_space_handle_t *);
void (*bs_free)(void *, bus_space_handle_t,
bus_size_t);
/* get kernel virtual address */
void * (*bs_vaddr)(void *, bus_space_handle_t);
/* mmap bus space for user */
paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int);
/* barrier */
void (*bs_barrier)(void *, bus_space_handle_t,
bus_size_t, bus_size_t, int);
/* read (single) */
uint8_t (*bs_r_1)(void *, bus_space_handle_t,
bus_size_t);
uint16_t (*bs_r_2)(void *, bus_space_handle_t,
bus_size_t);
uint32_t (*bs_r_4)(void *, bus_space_handle_t,
bus_size_t);
uint64_t (*bs_r_8)(void *, bus_space_handle_t,
bus_size_t);
/* read multiple */
void (*bs_rm_1)(void *, bus_space_handle_t,
bus_size_t, uint8_t *, bus_size_t);
void (*bs_rm_2)(void *, bus_space_handle_t,
bus_size_t, uint16_t *, bus_size_t);
void (*bs_rm_4)(void *, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void (*bs_rm_8)(void *, bus_space_handle_t,
bus_size_t, uint64_t *, bus_size_t);
/* read region */
void (*bs_rr_1)(void *, bus_space_handle_t,
bus_size_t, uint8_t *, bus_size_t);
void (*bs_rr_2)(void *, bus_space_handle_t,
bus_size_t, uint16_t *, bus_size_t);
void (*bs_rr_4)(void *, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void (*bs_rr_8)(void *, bus_space_handle_t,
bus_size_t, uint64_t *, bus_size_t);
/* write (single) */
void (*bs_w_1)(void *, bus_space_handle_t,
bus_size_t, uint8_t);
void (*bs_w_2)(void *, bus_space_handle_t,
bus_size_t, uint16_t);
void (*bs_w_4)(void *, bus_space_handle_t,
bus_size_t, uint32_t);
void (*bs_w_8)(void *, bus_space_handle_t,
bus_size_t, uint64_t);
/* write multiple */
void (*bs_wm_1)(void *, bus_space_handle_t,
bus_size_t, const uint8_t *, bus_size_t);
void (*bs_wm_2)(void *, bus_space_handle_t,
bus_size_t, const uint16_t *, bus_size_t);
void (*bs_wm_4)(void *, bus_space_handle_t,
bus_size_t, const uint32_t *, bus_size_t);
void (*bs_wm_8)(void *, bus_space_handle_t,
bus_size_t, const uint64_t *, bus_size_t);
/* write region */
void (*bs_wr_1)(void *, bus_space_handle_t,
bus_size_t, const uint8_t *, bus_size_t);
void (*bs_wr_2)(void *, bus_space_handle_t,
bus_size_t, const uint16_t *, bus_size_t);
void (*bs_wr_4)(void *, bus_space_handle_t,
bus_size_t, const uint32_t *, bus_size_t);
void (*bs_wr_8)(void *, bus_space_handle_t,
bus_size_t, const uint64_t *, bus_size_t);
/* set multiple */
void (*bs_sm_1)(void *, bus_space_handle_t,
bus_size_t, uint8_t, bus_size_t);
void (*bs_sm_2)(void *, bus_space_handle_t,
bus_size_t, uint16_t, bus_size_t);
void (*bs_sm_4)(void *, bus_space_handle_t,
bus_size_t, uint32_t, bus_size_t);
void (*bs_sm_8)(void *, bus_space_handle_t,
bus_size_t, uint64_t, bus_size_t);
/* set region */
void (*bs_sr_1)(void *, bus_space_handle_t,
bus_size_t, uint8_t, bus_size_t);
void (*bs_sr_2)(void *, bus_space_handle_t,
bus_size_t, uint16_t, bus_size_t);
void (*bs_sr_4)(void *, bus_space_handle_t,
bus_size_t, uint32_t, bus_size_t);
void (*bs_sr_8)(void *, bus_space_handle_t,
bus_size_t, uint64_t, bus_size_t);
/* copy */
void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t,
bus_space_handle_t, bus_size_t, bus_size_t);
void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t,
bus_space_handle_t, bus_size_t, bus_size_t);
void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t,
bus_space_handle_t, bus_size_t, bus_size_t);
void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t,
bus_space_handle_t, bus_size_t, bus_size_t);
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
/* read stream (single) */
uint8_t (*bs_r_1_s)(void *, bus_space_handle_t,
bus_size_t);
uint16_t (*bs_r_2_s)(void *, bus_space_handle_t,
bus_size_t);
uint32_t (*bs_r_4_s)(void *, bus_space_handle_t,
bus_size_t);
uint64_t (*bs_r_8_s)(void *, bus_space_handle_t,
bus_size_t);
/* read multiple stream */
void (*bs_rm_1_s)(void *, bus_space_handle_t,
bus_size_t, uint8_t *, bus_size_t);
void (*bs_rm_2_s)(void *, bus_space_handle_t,
bus_size_t, uint16_t *, bus_size_t);
void (*bs_rm_4_s)(void *, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void (*bs_rm_8_s)(void *, bus_space_handle_t,
bus_size_t, uint64_t *, bus_size_t);
/* read region stream */
void (*bs_rr_1_s)(void *, bus_space_handle_t,
bus_size_t, uint8_t *, bus_size_t);
void (*bs_rr_2_s)(void *, bus_space_handle_t,
bus_size_t, uint16_t *, bus_size_t);
void (*bs_rr_4_s)(void *, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void (*bs_rr_8_s)(void *, bus_space_handle_t,
bus_size_t, uint64_t *, bus_size_t);
/* write stream (single) */
void (*bs_w_1_s)(void *, bus_space_handle_t,
bus_size_t, uint8_t);
void (*bs_w_2_s)(void *, bus_space_handle_t,
bus_size_t, uint16_t);
void (*bs_w_4_s)(void *, bus_space_handle_t,
bus_size_t, uint32_t);
void (*bs_w_8_s)(void *, bus_space_handle_t,
bus_size_t, uint64_t);
/* write multiple stream */
void (*bs_wm_1_s)(void *, bus_space_handle_t,
bus_size_t, const uint8_t *, bus_size_t);
void (*bs_wm_2_s)(void *, bus_space_handle_t,
bus_size_t, const uint16_t *, bus_size_t);
void (*bs_wm_4_s)(void *, bus_space_handle_t,
bus_size_t, const uint32_t *, bus_size_t);
void (*bs_wm_8_s)(void *, bus_space_handle_t,
bus_size_t, const uint64_t *, bus_size_t);
/* write region stream */
void (*bs_wr_1_s)(void *, bus_space_handle_t,
bus_size_t, const uint8_t *, bus_size_t);
void (*bs_wr_2_s)(void *, bus_space_handle_t,
bus_size_t, const uint16_t *, bus_size_t);
void (*bs_wr_4_s)(void *, bus_space_handle_t,
bus_size_t, const uint32_t *, bus_size_t);
void (*bs_wr_8_s)(void *, bus_space_handle_t,
bus_size_t, const uint64_t *, bus_size_t);
#endif /* __BUS_SPACE_HAS_STREAM_METHODS */
};
#define BUS_SPACE_BARRIER_READ 0x01
#define BUS_SPACE_BARRIER_WRITE 0x02
#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
/* Bus Space DMA macros */
/*
* Flags used in various bus DMA methods.
*/
#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
#define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */
#define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */
#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
#define BUS_DMA_BUS2 0x020
#define BUS_DMA_BUS3 0x040
#define BUS_DMA_BUS4 0x080
#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
/*
* Private flags stored in the DMA map.
*/
#define _BUS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */
#define _BUS_DMAMAP_IS_BOUNCING 0x20000 /* is bouncing current xfer */
#define _BUS_DMAMAP_NOALLOC 0x40000 /* don't alloc memory from this range */
/* Forwards needed by prototypes below. */
struct mbuf;
struct uio;
/*
* Operations performed by bus_dmamap_sync().
*/
#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
typedef struct arm32_bus_dma_tag *bus_dma_tag_t;
typedef struct arm32_bus_dmamap *bus_dmamap_t;
#define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0)
/*
* bus_dma_segment_t
*
* Describes a single contiguous DMA transaction. Values
* are suitable for programming into DMA registers.
*/
struct arm32_bus_dma_segment {
/*
* PUBLIC MEMBERS: these are used by machine-independent code.
*/
bus_addr_t ds_addr; /* DMA address */
bus_size_t ds_len; /* length of transfer */
uint32_t _ds_flags; /* _BUS_DMAMAP_COHERENT */
};
typedef struct arm32_bus_dma_segment bus_dma_segment_t;
/*
* arm32_dma_range
*
* This structure describes a valid DMA range.
*/
struct arm32_dma_range {
bus_addr_t dr_sysbase; /* system base address */
bus_addr_t dr_busbase; /* appears here on bus */
bus_size_t dr_len; /* length of range */
uint32_t dr_flags; /* flags for range */
};
/*
* bus_dma_tag_t
*
* A machine-dependent opaque type describing the implementation of
* DMA for a given bus.
*/
struct arm32_bus_dma_tag {
/*
* DMA range for this tag. If the page doesn't fall within
* one of these ranges, an error is returned. The caller
* may then decide what to do with the transfer. If the
* range pointer is NULL, it is ignored.
*/
struct arm32_dma_range *_ranges;
int _nranges;
/*
* Opaque cookie for use by back-end.
*/
void *_cookie;
/*
* DMA mapping methods.
*/
int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
bus_size_t, bus_size_t, int, bus_dmamap_t *);
void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
bus_size_t, struct proc *, int);
int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
struct mbuf *, int);
int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
struct uio *, int);
int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
bus_dma_segment_t *, int, bus_size_t, int);
void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
void (*_dmamap_sync_pre)(bus_dma_tag_t, bus_dmamap_t,
bus_addr_t, bus_size_t, int);
void (*_dmamap_sync_post)(bus_dma_tag_t, bus_dmamap_t,
bus_addr_t, bus_size_t, int);
/*
* DMA memory utility functions.
*/
int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
bus_size_t, bus_dma_segment_t *, int, int *, int);
void (*_dmamem_free)(bus_dma_tag_t,
bus_dma_segment_t *, int);
int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
int, size_t, void **, int);
void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t);
paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
int, off_t, int, int);
/*
* DMA tag utility functions
*/
int (*_dmatag_subregion)(bus_dma_tag_t, bus_addr_t, bus_addr_t,
bus_dma_tag_t *, int);
void (*_dmatag_destroy)(bus_dma_tag_t);
/*
* State for bounce buffers
*/
int _tag_needs_free;
int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *);
};
/*
* bus_dmamap_t
*
* Describes a DMA mapping.
*/
struct arm32_bus_dmamap {
/*
* PRIVATE MEMBERS: not for use by machine-independent code.
*/
bus_size_t _dm_size; /* largest DMA transfer mappable */
int _dm_segcnt; /* number of segs this map can map */
bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */
bus_size_t _dm_boundary; /* don't cross this */
int _dm_flags; /* misc. flags */
void *_dm_origbuf; /* pointer to original buffer */
int _dm_buftype; /* type of buffer */
struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */
void *_dm_cookie; /* cookie for bus-specific functions */
/*
* PUBLIC MEMBERS: these are used by machine-independent code.
*/
bus_size_t dm_maxsegsz; /* largest possible segment */
bus_size_t dm_mapsize; /* size of the mapping */
int dm_nsegs; /* # valid segments in mapping */
bus_dma_segment_t dm_segs[1]; /* segments; variable length */
};
/* _dm_buftype */
#define _BUS_DMA_BUFTYPE_INVALID 0
#define _BUS_DMA_BUFTYPE_LINEAR 1
#define _BUS_DMA_BUFTYPE_MBUF 2
#define _BUS_DMA_BUFTYPE_UIO 3
#define _BUS_DMA_BUFTYPE_RAW 4
#ifdef _ARM32_BUS_DMA_PRIVATE
#define _BUS_AVAIL_END physical_end
/*
* Cookie used for bounce buffers. A pointer to one of these it stashed in
* the DMA map.
*/
struct arm32_bus_dma_cookie {
int id_flags; /* flags; see below */
/*
* Information about the original buffer used during
* DMA map syncs. Note that origibuflen is only used
* for ID_BUFTYPE_LINEAR.
*/
union {
void *un_origbuf; /* pointer to orig buffer if
bouncing */
char *un_linearbuf;
struct mbuf *un_mbuf;
struct uio *un_uio;
} id_origbuf_un;
#define id_origbuf id_origbuf_un.un_origbuf
#define id_origlinearbuf id_origbuf_un.un_linearbuf
#define id_origmbuf id_origbuf_un.un_mbuf
#define id_origuio id_origbuf_un.un_uio
bus_size_t id_origbuflen; /* ...and size */
void *id_bouncebuf; /* pointer to the bounce buffer */
bus_size_t id_bouncebuflen; /* ...and size */
int id_nbouncesegs; /* number of valid bounce segs */
bus_dma_segment_t id_bouncesegs[0]; /* array of bounce buffer
physical memory segments */
};
/* id_flags */
#define _BUS_DMA_IS_BOUNCING 0x04 /* is bouncing current xfer */
#define _BUS_DMA_HAS_BOUNCE 0x02 /* has bounce buffers */
#endif /* _ARM32_BUS_DMA_PRIVATE */
#define _BUS_DMA_MIGHT_NEED_BOUNCE 0x01 /* may need bounce buffers */
#endif /* _ARM_BUS_DEFS_H_ */

695
sys/arch/arm/include/bus_funcs.h
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@ -1,695 +0,0 @@
/* $NetBSD: bus_funcs.h,v 1.6 2014/01/29 00:42:15 matt Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_BUS_FUNCS_H_
#define _ARM_BUS_FUNCS_H_
#ifdef _KERNEL_OPT
#include "opt_cputypes.h"
#endif
/*
* Utility macros; INTERNAL USE ONLY.
*/
#define __bs_c(a,b) __CONCAT(a,b)
#define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size)
#define __bs_rs(sz, t, h, o) \
(*(t)->__bs_opname(r,sz))((t)->bs_cookie, h, o)
#define __bs_ws(sz, t, h, o, v) \
(*(t)->__bs_opname(w,sz))((t)->bs_cookie, h, o, v)
#define __bs_nonsingle(type, sz, t, h, o, a, c) \
(*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, a, c)
#define __bs_set(type, sz, t, h, o, v, c) \
(*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, v, c)
#define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \
(*(t)->__bs_opname(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt)
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
#define __bs_opname_s(op,size) __bs_c(__bs_c(__bs_c(__bs_c(bs_,op),_),size),_s)
#define __bs_rs_s(sz, t, h, o) \
(*(t)->__bs_opname_s(r,sz))((t)->bs_cookie, h, o)
#define __bs_ws_s(sz, t, h, o, v) \
(*(t)->__bs_opname_s(w,sz))((t)->bs_cookie, h, o, v)
#define __bs_nonsingle_s(type, sz, t, h, o, a, c) \
(*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, a, c)
#define __bs_set_s(type, sz, t, h, o, v, c) \
(*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, v, c)
#define __bs_copy_s(sz, t, h1, o1, h2, o2, cnt) \
(*(t)->__bs_opname_s(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt)
#endif
/*
* Mapping and unmapping operations.
*/
#define bus_space_map(t, a, s, c, hp) \
(*(t)->bs_map)((t)->bs_cookie, (a), (s), (c), (hp))
#define bus_space_unmap(t, h, s) \
(*(t)->bs_unmap)((t)->bs_cookie, (h), (s))
#define bus_space_subregion(t, h, o, s, hp) \
(*(t)->bs_subregion)((t)->bs_cookie, (h), (o), (s), (hp))
/*
* Allocation and deallocation operations.
*/
#define bus_space_alloc(t, rs, re, s, a, b, c, ap, hp) \
(*(t)->bs_alloc)((t)->bs_cookie, (rs), (re), (s), (a), (b), \
(c), (ap), (hp))
#define bus_space_free(t, h, s) \
(*(t)->bs_free)((t)->bs_cookie, (h), (s))
/*
* Get kernel virtual address for ranges mapped BUS_SPACE_MAP_LINEAR.
*/
#define bus_space_vaddr(t, h) \
(*(t)->bs_vaddr)((t)->bs_cookie, (h))
/*
* MMap bus space for a user application.
*/
#define bus_space_mmap(t, a, o, p, f) \
(*(t)->bs_mmap)((t)->bs_cookie, (a), (o), (p), (f))
/*
* Bus barrier operations.
*/
#define bus_space_barrier(t, h, o, l, f) \
(*(t)->bs_barrier)((t)->bs_cookie, (h), (o), (l), (f))
/*
* Bus read (single) operations.
*/
#define bus_space_read_1(t, h, o) __bs_rs(1,(t),(h),(o))
#define bus_space_read_2(t, h, o) __bs_rs(2,(t),(h),(o))
#define bus_space_read_4(t, h, o) __bs_rs(4,(t),(h),(o))
#define bus_space_read_8(t, h, o) __bs_rs(8,(t),(h),(o))
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
#define bus_space_read_stream_1(t, h, o) __bs_rs_s(1,(t),(h),(o))
#define bus_space_read_stream_2(t, h, o) __bs_rs_s(2,(t),(h),(o))
#define bus_space_read_stream_4(t, h, o) __bs_rs_s(4,(t),(h),(o))
#define bus_space_read_stream_8(t, h, o) __bs_rs_s(8,(t),(h),(o))
#endif
/*
* Bus read multiple operations.
*/
#define bus_space_read_multi_1(t, h, o, a, c) \
__bs_nonsingle(rm,1,(t),(h),(o),(a),(c))
#define bus_space_read_multi_2(t, h, o, a, c) \
__bs_nonsingle(rm,2,(t),(h),(o),(a),(c))
#define bus_space_read_multi_4(t, h, o, a, c) \
__bs_nonsingle(rm,4,(t),(h),(o),(a),(c))
#define bus_space_read_multi_8(t, h, o, a, c) \
__bs_nonsingle(rm,8,(t),(h),(o),(a),(c))
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
#define bus_space_read_multi_stream_1(t, h, o, a, c) \
__bs_nonsingle_s(rm,1,(t),(h),(o),(a),(c))
#define bus_space_read_multi_stream_2(t, h, o, a, c) \
__bs_nonsingle_s(rm,2,(t),(h),(o),(a),(c))
#define bus_space_read_multi_stream_4(t, h, o, a, c) \
__bs_nonsingle_s(rm,4,(t),(h),(o),(a),(c))
#define bus_space_read_multi_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c))
#endif
/*
* Bus read region operations.
*/
#define bus_space_read_region_1(t, h, o, a, c) \
__bs_nonsingle(rr,1,(t),(h),(o),(a),(c))
#define bus_space_read_region_2(t, h, o, a, c) \
__bs_nonsingle(rr,2,(t),(h),(o),(a),(c))
#define bus_space_read_region_4(t, h, o, a, c) \
__bs_nonsingle(rr,4,(t),(h),(o),(a),(c))
#define bus_space_read_region_8(t, h, o, a, c) \
__bs_nonsingle(rr,8,(t),(h),(o),(a),(c))
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
#define bus_space_read_region_stream_1(t, h, o, a, c) \
__bs_nonsingle_s(rr,1,(t),(h),(o),(a),(c))
#define bus_space_read_region_stream_2(t, h, o, a, c) \
__bs_nonsingle_s(rr,2,(t),(h),(o),(a),(c))
#define bus_space_read_region_stream_4(t, h, o, a, c) \
__bs_nonsingle_s(rr,4,(t),(h),(o),(a),(c))
#define bus_space_read_region_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c))
#endif
/*
* Bus write (single) operations.
*/
#define bus_space_write_1(t, h, o, v) __bs_ws(1,(t),(h),(o),(v))
#define bus_space_write_2(t, h, o, v) __bs_ws(2,(t),(h),(o),(v))
#define bus_space_write_4(t, h, o, v) __bs_ws(4,(t),(h),(o),(v))
#define bus_space_write_8(t, h, o, v) __bs_ws(8,(t),(h),(o),(v))
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
#define bus_space_write_stream_1(t, h, o, v) __bs_ws_s(1,(t),(h),(o),(v))
#define bus_space_write_stream_2(t, h, o, v) __bs_ws_s(2,(t),(h),(o),(v))
#define bus_space_write_stream_4(t, h, o, v) __bs_ws_s(4,(t),(h),(o),(v))
#define bus_space_write_stream_8(t, h, o, v) __bs_ws_s(8,(t),(h),(o),(v))
#endif
/*
* Bus write multiple operations.
*/
#define bus_space_write_multi_1(t, h, o, a, c) \
__bs_nonsingle(wm,1,(t),(h),(o),(a),(c))
#define bus_space_write_multi_2(t, h, o, a, c) \
__bs_nonsingle(wm,2,(t),(h),(o),(a),(c))
#define bus_space_write_multi_4(t, h, o, a, c) \
__bs_nonsingle(wm,4,(t),(h),(o),(a),(c))
#define bus_space_write_multi_8(t, h, o, a, c) \
__bs_nonsingle(wm,8,(t),(h),(o),(a),(c))
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
#define bus_space_write_multi_stream_1(t, h, o, a, c) \
__bs_nonsingle_s(wm,1,(t),(h),(o),(a),(c))
#define bus_space_write_multi_stream_2(t, h, o, a, c) \
__bs_nonsingle_s(wm,2,(t),(h),(o),(a),(c))
#define bus_space_write_multi_stream_4(t, h, o, a, c) \
__bs_nonsingle_s(wm,4,(t),(h),(o),(a),(c))
#define bus_space_write_multi_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c))
#endif
/*
* Bus write region operations.
*/
#define bus_space_write_region_1(t, h, o, a, c) \
__bs_nonsingle(wr,1,(t),(h),(o),(a),(c))
#define bus_space_write_region_2(t, h, o, a, c) \
__bs_nonsingle(wr,2,(t),(h),(o),(a),(c))
#define bus_space_write_region_4(t, h, o, a, c) \
__bs_nonsingle(wr,4,(t),(h),(o),(a),(c))
#define bus_space_write_region_8(t, h, o, a, c) \
__bs_nonsingle(wr,8,(t),(h),(o),(a),(c))
#ifdef __BUS_SPACE_HAS_STREAM_METHODS
#define bus_space_write_region_stream_1(t, h, o, a, c) \
__bs_nonsingle_s(wr,1,(t),(h),(o),(a),(c))
#define bus_space_write_region_stream_2(t, h, o, a, c) \
__bs_nonsingle_s(wr,2,(t),(h),(o),(a),(c))
#define bus_space_write_region_stream_4(t, h, o, a, c) \
__bs_nonsingle_s(wr,4,(t),(h),(o),(a),(c))
#define bus_space_write_region_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c))
#endif
/*
* Set multiple operations.
*/
#define bus_space_set_multi_1(t, h, o, v, c) \
__bs_set(sm,1,(t),(h),(o),(v),(c))
#define bus_space_set_multi_2(t, h, o, v, c) \
__bs_set(sm,2,(t),(h),(o),(v),(c))
#define bus_space_set_multi_4(t, h, o, v, c) \
__bs_set(sm,4,(t),(h),(o),(v),(c))
#define bus_space_set_multi_8(t, h, o, v, c) \
__bs_set(sm,8,(t),(h),(o),(v),(c))
/*
* Set region operations.
*/
#define bus_space_set_region_1(t, h, o, v, c) \
__bs_set(sr,1,(t),(h),(o),(v),(c))
#define bus_space_set_region_2(t, h, o, v, c) \
__bs_set(sr,2,(t),(h),(o),(v),(c))
#define bus_space_set_region_4(t, h, o, v, c) \
__bs_set(sr,4,(t),(h),(o),(v),(c))
#define bus_space_set_region_8(t, h, o, v, c) \
__bs_set(sr,8,(t),(h),(o),(v),(c))
/*
* Copy operations.
*/
#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \
__bs_copy(1, t, h1, o1, h2, o2, c)
#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \
__bs_copy(2, t, h1, o1, h2, o2, c)
#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \
__bs_copy(4, t, h1, o1, h2, o2, c)
#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \
__bs_copy(8, t, h1, o1, h2, o2, c)
/*
* Macros to provide prototypes for all the functions used in the
* bus_space structure
*/
#define bs_map_proto(f) \
int __bs_c(f,_bs_map)(void *t, bus_addr_t addr, \
bus_size_t size, int cacheable, bus_space_handle_t *bshp);
#define bs_unmap_proto(f) \
void __bs_c(f,_bs_unmap)(void *t, bus_space_handle_t bsh, \
bus_size_t size);
#define bs_subregion_proto(f) \
int __bs_c(f,_bs_subregion)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, bus_size_t size, \
bus_space_handle_t *nbshp);
#define bs_alloc_proto(f) \
int __bs_c(f,_bs_alloc)(void *t, bus_addr_t rstart, \
bus_addr_t rend, bus_size_t size, bus_size_t align, \
bus_size_t boundary, int cacheable, bus_addr_t *addrp, \
bus_space_handle_t *bshp);
#define bs_free_proto(f) \
void __bs_c(f,_bs_free)(void *t, bus_space_handle_t bsh, \
bus_size_t size);
#define bs_vaddr_proto(f) \
void * __bs_c(f,_bs_vaddr)(void *t, bus_space_handle_t bsh);
#define bs_mmap_proto(f) \
paddr_t __bs_c(f,_bs_mmap)(void *, bus_addr_t, off_t, int, int);
#define bs_barrier_proto(f) \
void __bs_c(f,_bs_barrier)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, bus_size_t len, int flags);
#define bs_r_1_proto(f) \
uint8_t __bs_c(f,_bs_r_1)(void *t, bus_space_handle_t bsh, \
bus_size_t offset);
#define bs_r_2_proto(f) \
uint16_t __bs_c(f,_bs_r_2)(void *t, bus_space_handle_t bsh, \
bus_size_t offset); \
uint16_t __bs_c(f,_bs_r_2_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset);
#define bs_r_4_proto(f) \
uint32_t __bs_c(f,_bs_r_4)(void *t, bus_space_handle_t bsh, \
bus_size_t offset); \
uint32_t __bs_c(f,_bs_r_4_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset);
#define bs_r_8_proto(f) \
uint64_t __bs_c(f,_bs_r_8)(void *t, bus_space_handle_t bsh, \
bus_size_t offset); \
uint64_t __bs_c(f,_bs_r_8_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset);
#define bs_w_1_proto(f) \
void __bs_c(f,_bs_w_1)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint8_t value);
#define bs_w_2_proto(f) \
void __bs_c(f,_bs_w_2)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t value); \
void __bs_c(f,_bs_w_2_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t value);
#define bs_w_4_proto(f) \
void __bs_c(f,_bs_w_4)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t value); \
void __bs_c(f,_bs_w_4_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t value);
#define bs_w_8_proto(f) \
void __bs_c(f,_bs_w_8)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t value); \
void __bs_c(f,_bs_w_8_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t value);
#define bs_rm_1_proto(f) \
void __bs_c(f,_bs_rm_1)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint8_t *addr, bus_size_t count);
#define bs_rm_2_proto(f) \
void __bs_c(f,_bs_rm_2)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t *addr, bus_size_t count); \
void __bs_c(f,_bs_rm_2_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t *addr, bus_size_t count);
#define bs_rm_4_proto(f) \
void __bs_c(f,_bs_rm_4)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t *addr, bus_size_t count); \
void __bs_c(f,_bs_rm_4_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t *addr, bus_size_t count);
#define bs_rm_8_proto(f) \
void __bs_c(f,_bs_rm_8)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t *addr, bus_size_t count); \
void __bs_c(f,_bs_rm_8_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t *addr, bus_size_t count);
#define bs_wm_1_proto(f) \
void __bs_c(f,_bs_wm_1)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint8_t *addr, bus_size_t count); \
#define bs_wm_2_proto(f) \
void __bs_c(f,_bs_wm_2)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint16_t *addr, bus_size_t count); \
void __bs_c(f,_bs_wm_2_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint16_t *addr, bus_size_t count);
#define bs_wm_4_proto(f) \
void __bs_c(f,_bs_wm_4)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint32_t *addr, bus_size_t count); \
void __bs_c(f,_bs_wm_4_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint32_t *addr, bus_size_t count);
#define bs_wm_8_proto(f) \
void __bs_c(f,_bs_wm_8)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint64_t *addr, bus_size_t count); \
void __bs_c(f,_bs_wm_8_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint64_t *addr, bus_size_t count);
#define bs_rr_1_proto(f) \
void __bs_c(f, _bs_rr_1)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint8_t *addr, bus_size_t count);
#define bs_rr_2_proto(f) \
void __bs_c(f, _bs_rr_2)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t *addr, bus_size_t count); \
void __bs_c(f, _bs_rr_2_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t *addr, bus_size_t count);
#define bs_rr_4_proto(f) \
void __bs_c(f, _bs_rr_4)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t *addr, bus_size_t count); \
void __bs_c(f, _bs_rr_4_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t *addr, bus_size_t count);
#define bs_rr_8_proto(f) \
void __bs_c(f, _bs_rr_8)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t *addr, bus_size_t count); \
void __bs_c(f, _bs_rr_8_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t *addr, bus_size_t count);
#define bs_wr_1_proto(f) \
void __bs_c(f, _bs_wr_1)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint8_t *addr, bus_size_t count);
#define bs_wr_2_proto(f) \
void __bs_c(f, _bs_wr_2)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint16_t *addr, bus_size_t count); \
void __bs_c(f, _bs_wr_2_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint16_t *addr, bus_size_t count);
#define bs_wr_4_proto(f) \
void __bs_c(f, _bs_wr_4)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint32_t *addr, bus_size_t count); \
void __bs_c(f, _bs_wr_4_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint32_t *addr, bus_size_t count);
#define bs_wr_8_proto(f) \
void __bs_c(f, _bs_wr_8)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint64_t *addr, bus_size_t count); \
void __bs_c(f, _bs_wr_8_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, const uint64_t *addr, bus_size_t count);
#define bs_sm_1_proto(f) \
void __bs_c(f,_bs_sm_1)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint8_t value, bus_size_t count);
#define bs_sm_2_proto(f) \
void __bs_c(f,_bs_sm_2)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t value, bus_size_t count);
#define bs_sm_4_proto(f) \
void __bs_c(f,_bs_sm_4)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t value, bus_size_t count);
#define bs_sm_8_proto(f) \
void __bs_c(f,_bs_sm_8)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t value, bus_size_t count);
#define bs_sr_1_proto(f) \
void __bs_c(f,_bs_sr_1)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint8_t value, bus_size_t count);
#define bs_sr_2_proto(f) \
void __bs_c(f,_bs_sr_2)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t value, bus_size_t count); \
void __bs_c(f,_bs_sr_2_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t value, bus_size_t count);
#define bs_sr_4_proto(f) \
void __bs_c(f,_bs_sr_4)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t value, bus_size_t count); \
void __bs_c(f,_bs_sr_4_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t value, bus_size_t count);
#define bs_sr_8_proto(f) \
void __bs_c(f,_bs_sr_8)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t value, bus_size_t count); \
void __bs_c(f,_bs_sr_8_swap)(void *t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t value, bus_size_t count);
#define bs_c_1_proto(f) \
void __bs_c(f,_bs_c_1)(void *t, bus_space_handle_t bsh1, \
bus_size_t offset1, bus_space_handle_t bsh2, \
bus_size_t offset2, bus_size_t count);
#define bs_c_2_proto(f) \
void __bs_c(f,_bs_c_2)(void *t, bus_space_handle_t bsh1, \
bus_size_t offset1, bus_space_handle_t bsh2, \
bus_size_t offset2, bus_size_t count);
#define bs_c_4_proto(f) \
void __bs_c(f,_bs_c_4)(void *t, bus_space_handle_t bsh1, \
bus_size_t offset1, bus_space_handle_t bsh2, \
bus_size_t offset2, bus_size_t count);
#define bs_c_8_proto(f) \
void __bs_c(f,_bs_c_8)(void *t, bus_space_handle_t bsh1, \
bus_size_t offset1, bus_space_handle_t bsh2, \
bus_size_t offset2, bus_size_t count);
#define bs_protos(f) \
bs_map_proto(f); \
bs_unmap_proto(f); \
bs_subregion_proto(f); \
bs_alloc_proto(f); \
bs_free_proto(f); \
bs_vaddr_proto(f); \
bs_mmap_proto(f); \
bs_barrier_proto(f); \
bs_r_1_proto(f); \
bs_r_2_proto(f); \
bs_r_4_proto(f); \
bs_r_8_proto(f); \
bs_w_1_proto(f); \
bs_w_2_proto(f); \
bs_w_4_proto(f); \
bs_w_8_proto(f); \
bs_rm_1_proto(f); \
bs_rm_2_proto(f); \
bs_rm_4_proto(f); \
bs_rm_8_proto(f); \
bs_wm_1_proto(f); \
bs_wm_2_proto(f); \
bs_wm_4_proto(f); \
bs_wm_8_proto(f); \
bs_rr_1_proto(f); \
bs_rr_2_proto(f); \
bs_rr_4_proto(f); \
bs_rr_8_proto(f); \
bs_wr_1_proto(f); \
bs_wr_2_proto(f); \
bs_wr_4_proto(f); \
bs_wr_8_proto(f); \
bs_sm_1_proto(f); \
bs_sm_2_proto(f); \
bs_sm_4_proto(f); \
bs_sm_8_proto(f); \
bs_sr_1_proto(f); \
bs_sr_2_proto(f); \
bs_sr_4_proto(f); \
bs_sr_8_proto(f); \
bs_c_1_proto(f); \
bs_c_2_proto(f); \
bs_c_4_proto(f); \
bs_c_8_proto(f);
/* Bus Space DMA macros */
/* Forwards needed by prototypes below. */
struct mbuf;
struct uio;
#define bus_dmamap_create(t, s, n, m, b, f, p) \
(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
#define bus_dmamap_destroy(t, p) \
(*(t)->_dmamap_destroy)((t), (p))
#define bus_dmamap_load(t, m, b, s, p, f) \
(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
#define bus_dmamap_load_mbuf(t, m, b, f) \
(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
#define bus_dmamap_load_uio(t, m, u, f) \
(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
#define bus_dmamap_unload(t, p) \
(*(t)->_dmamap_unload)((t), (p))
#define bus_dmamap_sync(t, p, o, l, ops) \
do { \
if (((p)->_dm_flags & (_BUS_DMAMAP_COHERENT|_BUS_DMAMAP_IS_BOUNCING)) == _BUS_DMAMAP_COHERENT) \
break; \
if (((ops) & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) != 0 \
&& (t)->_dmamap_sync_pre != NULL) \
(*(t)->_dmamap_sync_pre)((t), (p), (o), (l), (ops)); \
else if (((ops) & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) != 0 \
&& (t)->_dmamap_sync_post != NULL) \
(*(t)->_dmamap_sync_post)((t), (p), (o), (l), (ops)); \
} while (/*CONSTCOND*/0)
#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
(*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
#define bus_dmamem_free(t, sg, n) \
(*(t)->_dmamem_free)((t), (sg), (n))
#define bus_dmamem_map(t, sg, n, s, k, f) \
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
#define bus_dmamem_unmap(t, k, s) \
(*(t)->_dmamem_unmap)((t), (k), (s))
#define bus_dmamem_mmap(t, sg, n, o, p, f) \
(*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
#define bus_dmatag_subregion(t, mna, mxa, nt, f) \
(*(t)->_dmatag_subregion)((t), (mna), (mxa), (nt), (f))
#define bus_dmatag_destroy(t) \
(*(t)->_dmatag_destroy)(t)
#ifdef _ARM32_BUS_DMA_PRIVATE
extern paddr_t physical_start, physical_end;
int arm32_dma_range_intersect(struct arm32_dma_range *, int,
paddr_t pa, psize_t size, paddr_t *pap, psize_t *sizep);
int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
bus_size_t, int, bus_dmamap_t *);
void _bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
int _bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
bus_size_t, struct proc *, int);
int _bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t,
struct mbuf *, int);
int _bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t,
struct uio *, int);
int _bus_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
bus_dma_segment_t *, int, bus_size_t, int);
void _bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
bus_size_t, int);
#if defined(_ARM32_NEED_BUS_DMA_BOUNCE) || defined(CPU_CORTEX)
#define _BUS_DMAMAP_SYNC_FUNCS \
._dmamap_sync_pre = _bus_dmamap_sync, \
._dmamap_sync_post = _bus_dmamap_sync
#else
#define _BUS_DMAMAP_SYNC_FUNCS \
._dmamap_sync_pre = _bus_dmamap_sync
#endif
#define _BUS_DMAMAP_FUNCS \
._dmamap_create = _bus_dmamap_create, \
._dmamap_destroy = _bus_dmamap_destroy, \
._dmamap_load = _bus_dmamap_load, \
._dmamap_load_mbuf = _bus_dmamap_load_mbuf, \
._dmamap_load_raw = _bus_dmamap_load_raw, \
._dmamap_load_uio = _bus_dmamap_load_uio, \
._dmamap_unload = _bus_dmamap_unload, \
_BUS_DMAMAP_SYNC_FUNCS
int _bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size,
bus_size_t alignment, bus_size_t boundary,
bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags);
void _bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs,
int nsegs);
int _bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs,
int nsegs, size_t size, void **kvap, int flags);
void _bus_dmamem_unmap(bus_dma_tag_t tag, void *kva,
size_t size);
paddr_t _bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs,
int nsegs, off_t off, int prot, int flags);
#define _BUS_DMAMEM_FUNCS \
._dmamem_alloc = _bus_dmamem_alloc, \
._dmamem_free = _bus_dmamem_free, \
._dmamem_map = _bus_dmamem_map, \
._dmamem_unmap = _bus_dmamem_unmap, \
._dmamem_mmap = _bus_dmamem_mmap
int _bus_dmamem_alloc_range(bus_dma_tag_t tag, bus_size_t size,
bus_size_t alignment, bus_size_t boundary,
bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags,
vaddr_t low, vaddr_t high);
int _bus_dmatag_subregion(bus_dma_tag_t, bus_addr_t, bus_addr_t,
bus_dma_tag_t *, int);
void _bus_dmatag_destroy(bus_dma_tag_t);
#define _BUS_DMATAG_FUNCS \
._dmatag_subregion = _bus_dmatag_subregion, \
._dmatag_destroy = _bus_dmatag_destroy
#endif /* _ARM32_BUS_DMA_PRIVATE */
#endif /* _ARM_BUS_FUNCS_H_ */

121
sys/arch/arm/include/byte_swap.h
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@ -1,121 +0,0 @@
/* $NetBSD: byte_swap.h,v 1.13 2013/01/28 06:16:05 matt Exp $ */
/*-
* Copyright (c) 1997, 1999, 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Charles M. Hannum, Neil A. Carson, and Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_BYTE_SWAP_H_
#define _ARM_BYTE_SWAP_H_
#ifdef _LOCORE
#if defined(_ARM_ARCH_6) || defined(_ARM_ARCH_7)
#define BSWAP16(_src, _dst, _tmp) \
rev16 _dst, _src
#define BSWAP32(_src, _dst, _tmp) \
rev _dst, _src
#else
#define BSWAP16(_src, _dst, _tmp) \
mov _tmp, _src, ror #8 ;\
orr _tmp, _tmp, _tmp, lsr #16 ;\
bic _dst, _tmp, _tmp, lsl #16
#define BSWAP32(_src, _dst, _tmp) \
eor _tmp, _src, _src, ror #16 ;\
bic _tmp, _tmp, #0x00FF0000 ;\
mov _dst, _src, ror #8 ;\
eor _dst, _dst, _tmp, lsr #8
#endif
#else
#ifdef __GNUC__
#include <sys/types.h>
__BEGIN_DECLS
#define __BYTE_SWAP_U32_VARIABLE __byte_swap_u32_variable
static __inline uint32_t
__byte_swap_u32_variable(uint32_t v)
{
uint32_t t1;
#ifdef _ARM_ARCH_6
if (!__builtin_constant_p(v)) {
__asm("rev\t%0, %1" : "=r" (v) : "0" (v));
return v;
}
#endif
t1 = v ^ ((v << 16) | (v >> 16));
t1 &= 0xff00ffffU;
v = (v >> 8) | (v << 24);
v ^= (t1 >> 8);
return (v);
}
#define __BYTE_SWAP_U16_VARIABLE __byte_swap_u16_variable
static __inline uint16_t
__byte_swap_u16_variable(uint16_t v)
{
#ifdef _ARM_ARCH_6
if (!__builtin_constant_p(v)) {
uint32_t v32 = v;
__asm("rev16\t%0, %1" : "=r" (v32) : "0" (v32));
return v32;
}
#elif !defined(__thumb__) && 0 /* gcc produces decent code for this */
if (!__builtin_constant_p(v)) {
uint32_t v0 = v;
__asm volatile(
"mov %0, %1, ror #8\n"
"orr %0, %0, %0, lsr #16\n"
"bic %0, %0, %0, lsl #16"
: "=&r" (v0)
: "0" (v0));
return v0;
}
#endif
v &= 0xffff;
v = (v >> 8) | (v << 8);
return (v);
}
__END_DECLS
#endif
#endif /* _LOCORE */
#endif /* _ARM_BYTE_SWAP_H_ */

62
sys/arch/arm/include/cdefs.h
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@ -1,62 +0,0 @@
/* $NetBSD: cdefs.h,v 1.15 2014/06/23 03:40:57 christos Exp $ */
#ifndef _ARM_CDEFS_H_
#define _ARM_CDEFS_H_
#ifndef __lint__
#if (__GNUC__ == 4 && __GNUC_MINOR__ < 1) || __GNUC__ < 4
#error GCC 4.1 or compatible required.
#endif
#endif
#if defined (__ARM_ARCH_8A__)
#define _ARM_ARCH_8 /* ARMv8 64-bit in AARCH32 */
#endif
#if defined (_ARM_ARCH_8) || defined (__ARM_ARCH_7__) || \
defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__) || \
defined (__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
/* 7R, 7M, 7EM are for non MMU arms */
#define _ARM_ARCH_7
#endif
#if defined (_ARM_ARCH_7) || defined (__ARM_ARCH_6T2__)
#define _ARM_ARCH_T2 /* Thumb2 */
#endif
#if defined (_ARM_ARCH_T2) || defined (__ARM_ARCH_6__) || \
defined (__ARM_ARCH_6J__) || defined (__ARM_ARCH_6K__) || \
defined (__ARM_ARCH_6Z__) || defined (__ARM_ARCH_6ZK__) || \
defined (__ARM_ARCH_6ZM__)
#define _ARM_ARCH_6
#endif
#if defined (_ARM_ARCH_6) || defined (__ARM_ARCH_5T__) || \
defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5TEJ__)
#define _ARM_ARCH_5T
#endif
#if defined (_ARM_ARCH_6) || defined (_ARM_ARCH_5T) || defined (__ARM_ARCH_5__)
#define _ARM_ARCH_5
#endif
#if defined (_ARM_ARCH_5) || defined (__ARM_ARCH_4T__)
#define _ARM_ARCH_4T
#endif
#if defined (_ARM_ARCH_T2) || \
(!defined (__thumb__) && \
(defined (_ARM_ARCH_6) || defined (__ARM_ARCH_5TE__) || \
defined (__ARM_ARCH_5TEJ__)))
#define _ARM_ARCH_DWORD_OK
#endif
#if defined(__ARM_PCS_AAPCS64)
#define __ALIGNBYTES (sizeof(__int128_t) - 1)
#elif defined(__ARM_EABI__)
#define __ALIGNBYTES (sizeof(long long) - 1)
#else
#define __ALIGNBYTES (sizeof(int) - 1)
#endif
#endif /* !_ARM_CDEFS_H_ */

3
sys/arch/arm/include/common/fenv.h
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@ -1,3 +0,0 @@
/* $NetBSD: fenv.h,v 1.1 2013/05/01 12:01:55 matt Exp $ */
#include <arm/fenv.h>

326
sys/arch/arm/include/cpu.h
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@ -1,326 +0,0 @@
/* cpu.h,v 1.45.4.7 2008/01/28 18:20:39 matt Exp */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* cpu.h
*
* CPU specific symbols
*
* Created : 18/09/94
*
* Based on kate/katelib/arm6.h
*/
#ifndef _ARM_CPU_H_
#define _ARM_CPU_H_
/*
* User-visible definitions
*/
/* CTL_MACHDEP definitions. */
#define CPU_DEBUG 1 /* int: misc kernel debug control */
#define CPU_BOOTED_DEVICE 2 /* string: device we booted from */
#define CPU_BOOTED_KERNEL 3 /* string: kernel we booted */
#define CPU_CONSDEV 4 /* struct: dev_t of our console */
#define CPU_POWERSAVE 5 /* int: use CPU powersave mode */
#define CPU_MAXID 6 /* number of valid machdep ids */
#if defined(_KERNEL) || defined(_KMEMUSER)
/*
* Kernel-only definitions
*/
#if !defined(_MODULE) && defined(_KERNEL_OPT)
#include "opt_multiprocessor.h"
#include "opt_cpuoptions.h"
#include "opt_lockdebug.h"
#include "opt_cputypes.h"
#endif /* !_MODULE && _KERNEL_OPT */
#ifndef _LOCORE
#if defined(TPIDRPRW_IS_CURLWP) || defined(TPIDRPRW_IS_CURCPU)
#include <arm/armreg.h>
#endif
/* 1 == use cpu_sleep(), 0 == don't */
extern int cpu_do_powersave;
extern int cpu_fpu_present;
/* All the CLKF_* macros take a struct clockframe * as an argument. */
/*
* CLKF_USERMODE: Return TRUE/FALSE (1/0) depending on whether the
* frame came from USR mode or not.
*/
#ifdef __PROG32
#define CLKF_USERMODE(cf) (((cf)->cf_tf.tf_spsr & PSR_MODE) == PSR_USR32_MODE)
#else
#define CLKF_USERMODE(cf) (((cf)->cf_if.if_r15 & R15_MODE) == R15_MODE_USR)
#endif
/*
* CLKF_INTR: True if we took the interrupt from inside another
* interrupt handler.
*/
#if defined(__PROG32) && !defined(__ARM_EABI__)
/* Hack to treat FPE time as interrupt time so we can measure it */
#define CLKF_INTR(cf) \
((curcpu()->ci_intr_depth > 1) || \
((cf)->cf_tf.tf_spsr & PSR_MODE) == PSR_UND32_MODE)
#else
#define CLKF_INTR(cf) ((void)(cf), curcpu()->ci_intr_depth > 1)
#endif
/*
* CLKF_PC: Extract the program counter from a clockframe
*/
#ifdef __PROG32
#define CLKF_PC(frame) (frame->cf_tf.tf_pc)
#else
#define CLKF_PC(frame) (frame->cf_if.if_r15 & R15_PC)
#endif
/*
* LWP_PC: Find out the program counter for the given lwp.
*/
#ifdef __PROG32
#define LWP_PC(l) (lwp_trapframe(l)->tf_pc)
#else
#define LWP_PC(l) (lwp_trapframe(l)->tf_r15 & R15_PC)
#endif
/*
* Per-CPU information. For now we assume one CPU.
*/
#ifdef _KERNEL
static inline int curcpl(void);
static inline void set_curcpl(int);
static inline void cpu_dosoftints(void);
#endif
#ifdef _KMEMUSER
#include <sys/intr.h>
#endif
#include <sys/atomic.h>
#include <sys/cpu_data.h>
#include <sys/device_if.h>
#include <sys/evcnt.h>
struct cpu_info {
struct cpu_data ci_data; /* MI per-cpu data */
device_t ci_dev; /* Device corresponding to this CPU */
cpuid_t ci_cpuid;
uint32_t ci_arm_cpuid; /* aggregate CPU id */
uint32_t ci_arm_cputype; /* CPU type */
uint32_t ci_arm_cpurev; /* CPU revision */
uint32_t ci_ctrl; /* The CPU control register */
int ci_cpl; /* current processor level (spl) */
volatile int ci_astpending; /* */
int ci_want_resched; /* resched() was called */
int ci_intr_depth; /* */
struct cpu_softc *ci_softc; /* platform softc */
lwp_t *ci_softlwps[SOFTINT_COUNT];
volatile uint32_t ci_softints;
lwp_t *ci_curlwp; /* current lwp */
lwp_t *ci_lastlwp; /* last lwp */
struct evcnt ci_arm700bugcount;
int32_t ci_mtx_count;
int ci_mtx_oldspl;
register_t ci_undefsave[3];
uint32_t ci_vfp_id;
uint64_t ci_lastintr;
struct pmap_tlb_info *ci_tlb_info;
struct pmap *ci_pmap_lastuser;
struct pmap *ci_pmap_cur;
tlb_asid_t ci_pmap_asid_cur;
struct trapframe *ci_ddb_regs;
struct evcnt ci_abt_evs[16];
struct evcnt ci_und_ev;
struct evcnt ci_und_cp15_ev;
struct evcnt ci_vfp_evs[3];
#if defined(MP_CPU_INFO_MEMBERS)
MP_CPU_INFO_MEMBERS
#endif
};
extern struct cpu_info cpu_info_store;
struct lwp *arm_curlwp(void);
struct cpu_info *arm_curcpu(void);
#if defined(_MODULE)
#define curlwp arm_curlwp()
#define curcpu() arm_curcpu()
#elif defined(TPIDRPRW_IS_CURLWP)
static inline struct lwp *
_curlwp(void)
{
return (struct lwp *) armreg_tpidrprw_read();
}
static inline void
_curlwp_set(struct lwp *l)
{
armreg_tpidrprw_write((uintptr_t)l);
}
// Also in <sys/lwp.h> but also here if this was included before <sys/lwp.h>
static inline struct cpu_info *lwp_getcpu(struct lwp *);
#define curlwp _curlwp()
// curcpu() expands into two instructions: a mrc and a ldr
#define curcpu() lwp_getcpu(_curlwp())
#elif defined(TPIDRPRW_IS_CURCPU)
#ifdef __HAVE_PREEMPTION
#error __HAVE_PREEMPTION requires TPIDRPRW_IS_CURLWP
#endif
static inline struct cpu_info *
curcpu(void)
{
return (struct cpu_info *) armreg_tpidrprw_read();
}
#elif !defined(MULTIPROCESSOR)
#define curcpu() (&cpu_info_store)
#elif !defined(__HAVE_PREEMPTION)
#error MULTIPROCESSOR && !__HAVE_PREEMPTION requires TPIDRPRW_IS_CURCPU or TPIDRPRW_IS_CURLWP
#else
#error MULTIPROCESSOR && __HAVE_PREEMPTION requires TPIDRPRW_IS_CURLWP
#endif /* !TPIDRPRW_IS_CURCPU && !TPIDRPRW_IS_CURLWP */
#ifndef curlwp
#define curlwp (curcpu()->ci_curlwp)
#endif
#define CPU_INFO_ITERATOR int
#if defined(MULTIPROCESSOR)
extern struct cpu_info *cpu_info[];
#define cpu_number() (curcpu()->ci_index)
void cpu_boot_secondary_processors(void);
#define CPU_IS_PRIMARY(ci) ((ci)->ci_index == 0)
#define CPU_INFO_FOREACH(cii, ci) \
cii = 0, ci = cpu_info[0]; cii < ncpu && (ci = cpu_info[cii]) != NULL; cii++
#else
#define cpu_number() 0
#define CPU_IS_PRIMARY(ci) true
#define CPU_INFO_FOREACH(cii, ci) \
cii = 0, __USE(cii), ci = curcpu(); ci != NULL; ci = NULL
#endif
#define LWP0_CPU_INFO (&cpu_info_store)
static inline int
curcpl(void)
{
return curcpu()->ci_cpl;
}
static inline void
set_curcpl(int pri)
{
curcpu()->ci_cpl = pri;
}
static inline void
cpu_dosoftints(void)
{
#ifdef __HAVE_FAST_SOFTINTS
void dosoftints(void);
#ifndef __HAVE_PIC_FAST_SOFTINTS
struct cpu_info * const ci = curcpu();
if (ci->ci_intr_depth == 0 && (ci->ci_softints >> ci->ci_cpl) > 0)
dosoftints();
#endif
#endif
}
#ifdef __PROG32
void cpu_proc_fork(struct proc *, struct proc *);
#else
#define cpu_proc_fork(p1, p2)
#endif
/*
* Scheduling glue
*/
#ifdef __HAVE_PREEMPTION
#define setsoftast(ci) atomic_or_uint(&(ci)->ci_astpending, __BIT(0))
#else
#define setsoftast(ci) ((ci)->ci_astpending = __BIT(0))
#endif
/*
* Notify the current process (p) that it has a signal pending,
* process as soon as possible.
*/
#define cpu_signotify(l) setsoftast((l)->l_cpu)
/*
* Give a profiling tick to the current process when the user profiling
* buffer pages are invalid. On the i386, request an ast to send us
* through trap(), marking the proc as needing a profiling tick.
*/
#define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, \
setsoftast((l)->l_cpu))
/* for preeemption. */
void cpu_set_curpri(int);
/*
* We've already preallocated the stack for the idlelwps for additional CPUs.
* This hook allows to return them.
*/
vaddr_t cpu_uarea_alloc_idlelwp(struct cpu_info *);
#ifndef acorn26
/*
* cpu device glue (belongs in cpuvar.h)
*/
void cpu_attach(device_t, cpuid_t);
#endif
#endif /* !_LOCORE */
#endif /* _KERNEL */
#endif /* !_ARM_CPU_H_ */

79
sys/arch/arm/include/cpu_counter.h
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@ -1,79 +0,0 @@
/* $NetBSD: cpu_counter.h,v 1.3 2014/02/26 01:54:10 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_CPU_COUNTER_H_
#define _ARM_CPU_COUNTER_H_
/*
* ARM specific support for CPU counter (ARM11 and Cortex only).
* If __HAVE_CPU_COUNTER is defined for any other CPU_*, it will crash.
*/
#ifdef _KERNEL
#include <sys/cpu.h>
#if defined(CPU_CORTEX) || defined(CPU_ARM11)
#define cpu_hascounter() (curcpu()->ci_data.cpu_cc_freq != 0)
#else
#define cpu_hascounter() false
#endif
#define cpu_counter() cpu_counter32()
#if defined(CPU_CORTEX) || defined(CPU_ARM11)
static __inline uint32_t
cpu_counter32(void)
{
#if defined(CPU_CORTEX) && defined(CPU_ARM11)
const bool cortex_p = CPU_ID_CORTEX_P(curcpu()->ci_arm_cpuid);
#elif defined(CPU_CORTEX)
const bool cortex_p = true;
#elif defined(CPU_ARM11)
const bool cortex_p = false;
#endif
if (cortex_p)
return armreg_pmccntr_read();
else
return armreg_pmccntrv6_read();
}
#endif
static __inline uint64_t
cpu_frequency(struct cpu_info *ci)
{
return ci->ci_data.cpu_cc_freq;
}
#endif /* _KERNEL */
#endif /* _ARM_CPU_COUNTER_H_ */

265
sys/arch/arm/include/cpuconf.h
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@ -1,265 +0,0 @@
/* $NetBSD: cpuconf.h,v 1.25 2015/07/08 15:18:04 skrll Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_CPUCONF_H_
#define _ARM_CPUCONF_H_
#if defined(_KERNEL_OPT)
#include "opt_cputypes.h"
#include "opt_cpuoptions.h"
#endif /* _KERNEL_OPT */
#if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270)
#define __CPU_XSCALE_PXA2XX
#endif
#ifdef CPU_XSCALE_PXA2X0
#warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270.
#endif
/*
* IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
* "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE
* YOU ARE ADDING SUPPORT FOR.
*/
#if 0
/*
* Step 1: Count the number of CPU types configured into the kernel.
*/
#if defined(_KERNEL_OPT)
#define CPU_NTYPES (defined(CPU_ARM2) + defined(CPU_ARM250) + \
defined(CPU_ARM3) + \
defined(CPU_ARM6) + defined(CPU_ARM7) + \
defined(CPU_ARM7TDMI) + \
defined(CPU_ARM8) + defined(CPU_ARM9) + \
defined(CPU_ARM9E) + \
defined(CPU_ARM10) + \
defined(CPU_ARM11) + \
defined(CPU_ARM1136) + \
defined(CPU_ARM1176) + \
defined(CPU_ARM11MPCORE) + \
defined(CPU_CORTEX) + \
defined(CPU_CORTEXA8) + \
defined(CPU_CORTEXA9) + \
defined(CPU_SA110) + defined(CPU_SA1100) + \
defined(CPU_SA1110) + \
defined(CPU_FA526) + \
defined(CPU_IXP12X0) + \
defined(CPU_XSCALE) + \
defined(CPU_SHEEVA))
#else
#define CPU_NTYPES 2
#endif /* _KERNEL_OPT */
#endif
/*
* Step 2: Determine which ARM architecture versions are configured.
*/
#if !defined(_KERNEL_OPT) || \
(defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
#define ARM_ARCH_2 1
#else
#define ARM_ARCH_2 0
#endif
#if !defined(_KERNEL_OPT) || \
(defined(CPU_ARM6) || defined(CPU_ARM7))
#define ARM_ARCH_3 1
#else
#define ARM_ARCH_3 0
#endif
#if !defined(_KERNEL_OPT) || \
(defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_FA526) || \
defined(CPU_SA1110) || defined(CPU_IXP12X0))
#define ARM_ARCH_4 1
#else
#define ARM_ARCH_4 0
#endif
#if !defined(_KERNEL_OPT) || \
(defined(CPU_ARM9E) || defined(CPU_ARM10) || \
defined(CPU_XSCALE) || defined(CPU_SHEEVA))
#define ARM_ARCH_5 1
#else
#define ARM_ARCH_5 0
#endif
#if defined(CPU_ARM11) || defined(CPU_ARM11MPCORE)
#define ARM_ARCH_6 1
#else
#define ARM_ARCH_6 0
#endif
#if defined(CPU_CORTEX) || defined(CPU_PJ4B)
#define ARM_ARCH_7 1
#else
#define ARM_ARCH_7 0
#endif
#define ARM_NARCH (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \
ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7)
#if ARM_NARCH == 0
#error ARM_NARCH is 0
#endif
#if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7
/*
* We could support Thumb code on v4T, but the lack of clean interworking
* makes that hard.
*/
#define THUMB_CODE
#endif
/*
* Step 3: Define which MMU classes are configured:
*
* ARM_MMU_MEMC Prehistoric, external memory controller
* and MMU for ARMv2 CPUs.
*
* ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6.
*
* ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic
* ARM MMU, but has no write-through cache mode.
*
* ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM
* MMU, but also has several extensions which
* require different PTE layout to use.
*
* ARM_MMU_V6C ARM v6 MMU in backward compatible mode.
* Compatible with generic ARM MMU, but
* also has several extensions which
* require different PTE layouts to use.
* XP bit in CP15 control reg is cleared.
*
* ARM_MMU_V6N ARM v6 MMU with XP bit of CP15 control reg
* set. New features such as shared-bit
* and excute-never bit are available.
* Multiprocessor support needs this mode.
*
* ARM_MMU_V7 ARM v7 MMU.
*/
#if !defined(_KERNEL_OPT) || \
(defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
#define ARM_MMU_MEMC 1
#else
#define ARM_MMU_MEMC 0
#endif
#if !defined(_KERNEL_OPT) || \
(defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \
defined(CPU_ARM10) || defined(CPU_FA526)) || defined(CPU_SHEEVA)
#define ARM_MMU_GENERIC 1
#else
#define ARM_MMU_GENERIC 0
#endif
#if !defined(_KERNEL_OPT) || \
(defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
defined(CPU_IXP12X0))
#define ARM_MMU_SA1 1
#else
#define ARM_MMU_SA1 0
#endif
#if !defined(_KERNEL_OPT) || \
defined(CPU_XSCALE)
#define ARM_MMU_XSCALE 1
#else
#define ARM_MMU_XSCALE 0
#endif
#if !defined(_KERNEL_OPT) || \
(defined(CPU_ARM11) && defined(ARM11_COMPAT_MMU))
#define ARM_MMU_V6C 1
#else
#define ARM_MMU_V6C 0
#endif
#if !defined(_KERNEL_OPT) || \
(defined(CPU_ARM11) && !defined(ARM11_COMPAT_MMU))
#define ARM_MMU_V6N 1
#else
#define ARM_MMU_V6N 0
#endif
#define ARM_MMU_V6 (ARM_MMU_V6C + ARM_MMU_V6N)
#if !defined(_KERNEL_OPT) || \
defined(CPU_ARMV7)
#define ARM_MMU_V7 1
#else
#define ARM_MMU_V7 0
#endif
/*
* Can we use the ASID support in armv6+ MMUs?
*/
#if !defined(_LOCORE)
#define ARM_MMU_EXTENDED ((ARM_MMU_MEMC + ARM_MMU_GENERIC \
+ ARM_MMU_SA1 + ARM_MMU_XSCALE \
+ ARM_MMU_V6C) == 0 \
&& (ARM_MMU_V6N + ARM_MMU_V7) > 0)
#if ARM_MMU_EXTENDED == 0
#undef ARM_MMU_EXTENDED
#endif
#endif
#define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \
ARM_MMU_SA1 + ARM_MMU_XSCALE + \
ARM_MMU_V6N + ARM_MMU_V6C + ARM_MMU_V7)
#if ARM_NMMUS == 0
#error ARM_NMMUS is 0
#endif
/*
* Step 4: Define features that may be present on a subset of CPUs
*
* ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321
*/
#if !defined(_KERNEL_OPT) || \
(defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321))
#define ARM_XSCALE_PMU 1
#else
#define ARM_XSCALE_PMU 0
#endif
#endif /* _ARM_CPUCONF_H_ */

450
sys/arch/arm/include/cpufunc.h
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@ -1,450 +0,0 @@
/* cpufunc.h,v 1.40.22.4 2007/11/08 10:59:33 matt Exp */
/*
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Causality Limited.
* 4. The name of Causality Limited may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* cpufunc.h
*
* Prototypes for cpu, mmu and tlb related functions.
*/
#ifndef _ARM_CPUFUNC_H_
#define _ARM_CPUFUNC_H_
#ifdef _KERNEL
#include <sys/types.h>
#include <arm/armreg.h>
#include <arm/cpuconf.h>
#include <arm/armreg.h>
#include <arm/cpufunc_proto.h>
struct cpu_functions {
/* CPU functions */
u_int (*cf_id) (void);
void (*cf_cpwait) (void);
/* MMU functions */
u_int (*cf_control) (u_int, u_int);
void (*cf_domains) (u_int);
#if defined(ARM_MMU_EXTENDED)
void (*cf_setttb) (u_int, tlb_asid_t);
#else
void (*cf_setttb) (u_int, bool);
#endif
u_int (*cf_faultstatus) (void);
u_int (*cf_faultaddress) (void);
/* TLB functions */
void (*cf_tlb_flushID) (void);
void (*cf_tlb_flushID_SE) (vaddr_t);
void (*cf_tlb_flushI) (void);
void (*cf_tlb_flushI_SE) (vaddr_t);
void (*cf_tlb_flushD) (void);
void (*cf_tlb_flushD_SE) (vaddr_t);
/*
* Cache operations:
*
* We define the following primitives:
*
* icache_sync_all Synchronize I-cache
* icache_sync_range Synchronize I-cache range
*
* dcache_wbinv_all Write-back and Invalidate D-cache
* dcache_wbinv_range Write-back and Invalidate D-cache range
* dcache_inv_range Invalidate D-cache range
* dcache_wb_range Write-back D-cache range
*
* idcache_wbinv_all Write-back and Invalidate D-cache,
* Invalidate I-cache
* idcache_wbinv_range Write-back and Invalidate D-cache,
* Invalidate I-cache range
*
* Note that the ARM term for "write-back" is "clean". We use
* the term "write-back" since it's a more common way to describe
* the operation.
*
* There are some rules that must be followed:
*
* I-cache Synch (all or range):
* The goal is to synchronize the instruction stream,
* so you may beed to write-back dirty D-cache blocks
* first. If a range is requested, and you can't
* synchronize just a range, you have to hit the whole
* thing.
*
* D-cache Write-Back and Invalidate range:
* If you can't WB-Inv a range, you must WB-Inv the
* entire D-cache.
*
* D-cache Invalidate:
* If you can't Inv the D-cache, you must Write-Back
* and Invalidate. Code that uses this operation
* MUST NOT assume that the D-cache will not be written
* back to memory.
*
* D-cache Write-Back:
* If you can't Write-back without doing an Inv,
* that's fine. Then treat this as a WB-Inv.
* Skipping the invalidate is merely an optimization.
*
* All operations:
* Valid virtual addresses must be passed to each
* cache operation.
*/
void (*cf_icache_sync_all) (void);
void (*cf_icache_sync_range) (vaddr_t, vsize_t);
void (*cf_dcache_wbinv_all) (void);
void (*cf_dcache_wbinv_range)(vaddr_t, vsize_t);
void (*cf_dcache_inv_range) (vaddr_t, vsize_t);
void (*cf_dcache_wb_range) (vaddr_t, vsize_t);
void (*cf_sdcache_wbinv_range)(vaddr_t, paddr_t, psize_t);
void (*cf_sdcache_inv_range) (vaddr_t, paddr_t, psize_t);
void (*cf_sdcache_wb_range) (vaddr_t, paddr_t, psize_t);
void (*cf_idcache_wbinv_all) (void);
void (*cf_idcache_wbinv_range)(vaddr_t, vsize_t);
/* Other functions */
void (*cf_flush_prefetchbuf) (void);
void (*cf_drain_writebuf) (void);
void (*cf_flush_brnchtgt_C) (void);
void (*cf_flush_brnchtgt_E) (u_int);
void (*cf_sleep) (int mode);
/* Soft functions */
int (*cf_dataabt_fixup) (void *);
int (*cf_prefetchabt_fixup) (void *);
#if defined(ARM_MMU_EXTENDED)
void (*cf_context_switch) (u_int, tlb_asid_t);
#else
void (*cf_context_switch) (u_int);
#endif
void (*cf_setup) (char *);
};
extern struct cpu_functions cpufuncs;
extern u_int cputype;
#define cpu_id() cpufuncs.cf_id()
#define cpu_control(c, e) cpufuncs.cf_control(c, e)
#define cpu_domains(d) cpufuncs.cf_domains(d)
#define cpu_setttb(t, f) cpufuncs.cf_setttb(t, f)
#define cpu_faultstatus() cpufuncs.cf_faultstatus()
#define cpu_faultaddress() cpufuncs.cf_faultaddress()
#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI()
#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e)
#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()
#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
#define cpu_sdcache_wbinv_range(a, b, s) cpufuncs.cf_sdcache_wbinv_range((a), (b), (s))
#define cpu_sdcache_inv_range(a, b, s) cpufuncs.cf_sdcache_inv_range((a), (b), (s))
#define cpu_sdcache_wb_range(a, b, s) cpufuncs.cf_sdcache_wb_range((a), (b), (s))
#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()
#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C()
#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e)
#define cpu_sleep(m) cpufuncs.cf_sleep(m)
#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a)
#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a)
#define ABORT_FIXUP_OK 0 /* fixup succeeded */
#define ABORT_FIXUP_FAILED 1 /* fixup failed */
#define ABORT_FIXUP_RETURN 2 /* abort handler should return */
#define cpu_context_switch(a) cpufuncs.cf_context_switch(a)
#define cpu_setup(a) cpufuncs.cf_setup(a)
int set_cpufuncs (void);
int set_cpufuncs_id (u_int);
#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
void cpufunc_nullop (void);
int cpufunc_null_fixup (void *);
int early_abort_fixup (void *);
int late_abort_fixup (void *);
u_int cpufunc_id (void);
u_int cpufunc_control (u_int, u_int);
void cpufunc_domains (u_int);
u_int cpufunc_faultstatus (void);
u_int cpufunc_faultaddress (void);
#define tlb_flush cpu_tlb_flushID
#define setttb cpu_setttb
#define drain_writebuf cpu_drain_writebuf
#if defined(CPU_XSCALE)
#define cpu_cpwait() cpufuncs.cf_cpwait()
#endif
#ifndef cpu_cpwait
#define cpu_cpwait()
#endif
/*
* Macros for manipulating CPU interrupts
*/
#ifdef __PROG32
static __inline uint32_t __set_cpsr_c(uint32_t bic, uint32_t eor) __attribute__((__unused__));
static __inline uint32_t disable_interrupts(uint32_t mask) __attribute__((__unused__));
static __inline uint32_t enable_interrupts(uint32_t mask) __attribute__((__unused__));
static __inline uint32_t
__set_cpsr_c(uint32_t bic, uint32_t eor)
{
uint32_t tmp, ret;
__asm volatile(
"mrs %0, cpsr\n" /* Get the CPSR */
"bic %1, %0, %2\n" /* Clear bits */
"eor %1, %1, %3\n" /* XOR bits */
"msr cpsr_c, %1\n" /* Set the control field of CPSR */
: "=&r" (ret), "=&r" (tmp)
: "r" (bic), "r" (eor) : "memory");
return ret;
}
static __inline uint32_t
disable_interrupts(uint32_t mask)
{
uint32_t tmp, ret;
mask &= (I32_bit | F32_bit);
__asm volatile(
"mrs %0, cpsr\n" /* Get the CPSR */
"orr %1, %0, %2\n" /* set bits */
"msr cpsr_c, %1\n" /* Set the control field of CPSR */
: "=&r" (ret), "=&r" (tmp)
: "r" (mask)
: "memory");
return ret;
}
static __inline uint32_t
enable_interrupts(uint32_t mask)
{
uint32_t ret;
mask &= (I32_bit | F32_bit);
/* Get the CPSR */
__asm __volatile("mrs\t%0, cpsr\n" : "=r"(ret));
#ifdef _ARM_ARCH_6
if (__builtin_constant_p(mask)) {
switch (mask) {
case I32_bit | F32_bit:
__asm __volatile("cpsie\tif");
break;
case I32_bit:
__asm __volatile("cpsie\ti");
break;
case F32_bit:
__asm __volatile("cpsie\tf");
break;
default:
break;
}
return ret;
}
#endif /* _ARM_ARCH_6 */
/* Set the control field of CPSR */
__asm volatile("msr\tcpsr_c, %0" :: "r"(ret & ~mask));
return ret;
}
#define restore_interrupts(old_cpsr) \
(__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
static inline void cpsie(register_t psw) __attribute__((__unused__));
static inline register_t cpsid(register_t psw) __attribute__((__unused__));
static inline void
cpsie(register_t psw)
{
#ifdef _ARM_ARCH_6
if (!__builtin_constant_p(psw)) {
enable_interrupts(psw);
return;
}
switch (psw & (I32_bit|F32_bit)) {
case I32_bit: __asm("cpsie\ti"); break;
case F32_bit: __asm("cpsie\tf"); break;
case I32_bit|F32_bit: __asm("cpsie\tif"); break;
}
#else
enable_interrupts(psw);
#endif
}
static inline register_t
cpsid(register_t psw)
{
#ifdef _ARM_ARCH_6
register_t oldpsw;
if (!__builtin_constant_p(psw))
return disable_interrupts(psw);
__asm("mrs %0, cpsr" : "=r"(oldpsw));
switch (psw & (I32_bit|F32_bit)) {
case I32_bit: __asm("cpsid\ti"); break;
case F32_bit: __asm("cpsid\tf"); break;
case I32_bit|F32_bit: __asm("cpsid\tif"); break;
}
return oldpsw;
#else
return disable_interrupts(psw);
#endif
}
#else /* ! __PROG32 */
#define disable_interrupts(mask) \
(set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \
(mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))
#define enable_interrupts(mask) \
(set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0))
#define restore_interrupts(old_r15) \
(set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \
(old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))
#endif /* __PROG32 */
#ifdef __PROG32
/* Functions to manipulate the CPSR. */
u_int SetCPSR(u_int, u_int);
u_int GetCPSR(void);
#else
/* Functions to manipulate the processor control bits in r15. */
u_int set_r15(u_int, u_int);
u_int get_r15(void);
#endif /* __PROG32 */
/*
* CPU functions from locore.S
*/
void cpu_reset (void) __dead;
/*
* Cache info variables.
*/
#define CACHE_TYPE_VIVT 0
#define CACHE_TYPE_xxPT 1
#define CACHE_TYPE_VIPT 1
#define CACHE_TYPE_PIxx 2
#define CACHE_TYPE_PIPT 3
/* PRIMARY CACHE VARIABLES */
struct arm_cache_info {
u_int icache_size;
u_int icache_line_size;
u_int icache_ways;
u_int icache_way_size;
u_int icache_sets;
u_int dcache_size;
u_int dcache_line_size;
u_int dcache_ways;
u_int dcache_way_size;
u_int dcache_sets;
uint8_t cache_type;
bool cache_unified;
uint8_t icache_type;
uint8_t dcache_type;
};
extern u_int arm_cache_prefer_mask;
extern u_int arm_dcache_align;
extern u_int arm_dcache_align_mask;
extern struct arm_cache_info arm_pcache;
extern struct arm_cache_info arm_scache;
#endif /* _KERNEL */
#if defined(_KERNEL) || defined(_KMEMUSER)
/*
* Miscellany
*/
int get_pc_str_offset (void);
/*
* Functions to manipulate cpu r13
* (in arm/arm32/setstack.S)
*/
void set_stackptr (u_int, u_int);
u_int get_stackptr (u_int);
#endif /* _KERNEL || _KMEMUSER */
#endif /* _ARM_CPUFUNC_H_ */
/* End of cpufunc.h */

424
sys/arch/arm/include/cpufunc_proto.h
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@ -1,424 +0,0 @@
/* cpufunc.h,v 1.40.22.4 2007/11/08 10:59:33 matt Exp */
/*
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Causality Limited.
* 4. The name of Causality Limited may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* cpufunc.h
*
* Prototypes for cpu, mmu and tlb related functions.
*/
#ifndef _ARM_CPUFUNC_PROTO_H_
#define _ARM_CPUFUNC_PROTO_H_
#ifdef _KERNEL
#include <sys/types.h>
#include <arm/armreg.h>
#include <arm/cpuconf.h>
#if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3)
void arm3_cache_flush (void);
#endif /* CPU_ARM2 || CPU_ARM250 || CPU_ARM3 */
#ifdef CPU_ARM2
u_int arm2_id (void);
#endif /* CPU_ARM2 */
#ifdef CPU_ARM250
u_int arm250_id (void);
#endif
#ifdef CPU_ARM3
u_int arm3_control (u_int, u_int);
#endif /* CPU_ARM3 */
#if defined(CPU_ARM6) || defined(CPU_ARM7)
void arm67_setttb (u_int, bool);
void arm67_tlb_flush (void);
void arm67_tlb_purge (vaddr_t);
void arm67_cache_flush (void);
void arm67_context_switch (u_int);
#endif /* CPU_ARM6 || CPU_ARM7 */
#ifdef CPU_ARM6
void arm6_setup (char *);
#endif /* CPU_ARM6 */
#ifdef CPU_ARM7
void arm7_setup (char *);
#endif /* CPU_ARM7 */
#ifdef CPU_ARM7TDMI
int arm7_dataabt_fixup (void *);
void arm7tdmi_setup (char *);
void arm7tdmi_setttb (u_int, bool);
void arm7tdmi_tlb_flushID (void);
void arm7tdmi_tlb_flushID_SE (vaddr_t);
void arm7tdmi_cache_flushID (void);
void arm7tdmi_context_switch (u_int);
#endif /* CPU_ARM7TDMI */
#ifdef CPU_ARM8
void arm8_setttb (u_int, bool);
void arm8_tlb_flushID (void);
void arm8_tlb_flushID_SE (vaddr_t);
void arm8_cache_flushID (void);
void arm8_cache_flushID_E (u_int);
void arm8_cache_cleanID (void);
void arm8_cache_cleanID_E (u_int);
void arm8_cache_purgeID (void);
void arm8_cache_purgeID_E (u_int entry);
void arm8_cache_syncI (void);
void arm8_cache_cleanID_rng (vaddr_t, vsize_t);
void arm8_cache_cleanD_rng (vaddr_t, vsize_t);
void arm8_cache_purgeID_rng (vaddr_t, vsize_t);
void arm8_cache_purgeD_rng (vaddr_t, vsize_t);
void arm8_cache_syncI_rng (vaddr_t, vsize_t);
void arm8_context_switch (u_int);
void arm8_setup (char *);
u_int arm8_clock_config (u_int, u_int);
#endif
#ifdef CPU_FA526
void fa526_setup (char *);
void fa526_setttb (u_int, bool);
void fa526_context_switch (u_int);
void fa526_cpu_sleep (int);
void fa526_tlb_flushI_SE (vaddr_t);
void fa526_tlb_flushID_SE (vaddr_t);
void fa526_flush_prefetchbuf (void);
void fa526_flush_brnchtgt_E (u_int);
void fa526_icache_sync_all (void);
void fa526_icache_sync_range(vaddr_t, vsize_t);
void fa526_dcache_wbinv_all (void);
void fa526_dcache_wbinv_range(vaddr_t, vsize_t);
void fa526_dcache_inv_range (vaddr_t, vsize_t);
void fa526_dcache_wb_range (vaddr_t, vsize_t);
void fa526_idcache_wbinv_all(void);
void fa526_idcache_wbinv_range(vaddr_t, vsize_t);
#endif
#ifdef CPU_SA110
void sa110_setup (char *);
void sa110_context_switch (u_int);
#endif /* CPU_SA110 */
#if defined(CPU_SA1100) || defined(CPU_SA1110)
void sa11x0_drain_readbuf (void);
void sa11x0_context_switch (u_int);
void sa11x0_cpu_sleep (int);
void sa11x0_setup (char *);
#endif
#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
void sa1_setttb (u_int, bool);
void sa1_tlb_flushID_SE (vaddr_t);
void sa1_cache_flushID (void);
void sa1_cache_flushI (void);
void sa1_cache_flushD (void);
void sa1_cache_flushD_SE (vaddr_t);
void sa1_cache_cleanID (void);
void sa1_cache_cleanD (void);
void sa1_cache_cleanD_E (u_int);
void sa1_cache_purgeID (void);
void sa1_cache_purgeID_E (u_int);
void sa1_cache_purgeD (void);
void sa1_cache_purgeD_E (u_int);
void sa1_cache_syncI (void);
void sa1_cache_cleanID_rng (vaddr_t, vsize_t);
void sa1_cache_cleanD_rng (vaddr_t, vsize_t);
void sa1_cache_purgeID_rng (vaddr_t, vsize_t);
void sa1_cache_purgeD_rng (vaddr_t, vsize_t);
void sa1_cache_syncI_rng (vaddr_t, vsize_t);
#endif
#ifdef CPU_ARM9
void arm9_setttb (u_int, bool);
void arm9_tlb_flushID_SE (vaddr_t);
void arm9_icache_sync_all (void);
void arm9_icache_sync_range (vaddr_t, vsize_t);
void arm9_dcache_wbinv_all (void);
void arm9_dcache_wbinv_range (vaddr_t, vsize_t);
void arm9_dcache_inv_range (vaddr_t, vsize_t);
void arm9_dcache_wb_range (vaddr_t, vsize_t);
void arm9_idcache_wbinv_all (void);
void arm9_idcache_wbinv_range (vaddr_t, vsize_t);
void arm9_context_switch (u_int);
void arm9_setup (char *);
extern unsigned arm9_dcache_sets_max;
extern unsigned arm9_dcache_sets_inc;
extern unsigned arm9_dcache_index_max;
extern unsigned arm9_dcache_index_inc;
#endif
#if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_SHEEVA)
void arm10_tlb_flushID_SE (vaddr_t);
void arm10_tlb_flushI_SE (vaddr_t);
void arm10_context_switch (u_int);
void arm10_setup (char *);
#endif
#if defined(CPU_ARM9E) || defined (CPU_ARM10) || defined(CPU_SHEEVA)
void armv5_ec_setttb (u_int, bool);
void armv5_ec_icache_sync_all (void);
void armv5_ec_icache_sync_range (vaddr_t, vsize_t);
void armv5_ec_dcache_wbinv_all (void);
void armv5_ec_dcache_wbinv_range (vaddr_t, vsize_t);
void armv5_ec_dcache_inv_range (vaddr_t, vsize_t);
void armv5_ec_dcache_wb_range (vaddr_t, vsize_t);
void armv5_ec_idcache_wbinv_all (void);
void armv5_ec_idcache_wbinv_range (vaddr_t, vsize_t);
#endif
#if defined (CPU_ARM10) || defined (CPU_ARM11MPCORE)
void armv5_setttb (u_int, bool);
void armv5_icache_sync_all (void);
void armv5_icache_sync_range (vaddr_t, vsize_t);
void armv5_dcache_wbinv_all (void);
void armv5_dcache_wbinv_range (vaddr_t, vsize_t);
void armv5_dcache_inv_range (vaddr_t, vsize_t);
void armv5_dcache_wb_range (vaddr_t, vsize_t);
void armv5_idcache_wbinv_all (void);
void armv5_idcache_wbinv_range (vaddr_t, vsize_t);
extern unsigned armv5_dcache_sets_max;
extern unsigned armv5_dcache_sets_inc;
extern unsigned armv5_dcache_index_max;
extern unsigned armv5_dcache_index_inc;
#endif
#if defined(CPU_ARM11MPCORE)
void arm11mpcore_setup (char *);
#endif
#if defined(CPU_ARM11)
#if defined(ARM_MMU_EXTENDED)
void arm11_setttb (u_int, tlb_asid_t);
void arm11_context_switch (u_int, tlb_asid_t);
#else
void arm11_setttb (u_int, bool);
void arm11_context_switch (u_int);
#endif
void arm11_cpu_sleep (int);
void arm11_setup (char *string);
void arm11_tlb_flushID (void);
void arm11_tlb_flushI (void);
void arm11_tlb_flushD (void);
void arm11_tlb_flushID_SE (vaddr_t);
void arm11_tlb_flushI_SE (vaddr_t);
void arm11_tlb_flushD_SE (vaddr_t);
void armv11_dcache_wbinv_all (void);
void armv11_idcache_wbinv_all(void);
void arm11_drain_writebuf (void);
void arm11_sleep (int);
void armv6_setttb (u_int, bool);
void armv6_icache_sync_all (void);
void armv6_icache_sync_range (vaddr_t, vsize_t);
void armv6_dcache_wbinv_all (void);
void armv6_dcache_wbinv_range (vaddr_t, vsize_t);
void armv6_dcache_inv_range (vaddr_t, vsize_t);
void armv6_dcache_wb_range (vaddr_t, vsize_t);
void armv6_idcache_wbinv_all (void);
void armv6_idcache_wbinv_range (vaddr_t, vsize_t);
#endif
#if defined(CPU_ARMV7)
#if defined(ARM_MMU_EXTENDED)
void armv7_setttb(u_int, tlb_asid_t);
void armv7_context_switch(u_int, tlb_asid_t);
#else
void armv7_setttb(u_int, bool);
void armv7_context_switch(u_int);
#endif
void armv7_icache_sync_range(vaddr_t, vsize_t);
void armv7_icache_sync_all(void);
void armv7_dcache_inv_range(vaddr_t, vsize_t);
void armv7_dcache_wb_range(vaddr_t, vsize_t);
void armv7_dcache_wbinv_range(vaddr_t, vsize_t);
void armv7_dcache_wbinv_all(void);
void armv7_idcache_wbinv_range(vaddr_t, vsize_t);
void armv7_idcache_wbinv_all(void);
void armv7_tlb_flushID(void);
void armv7_tlb_flushI(void);
void armv7_tlb_flushD(void);
void armv7_tlb_flushID_SE(vaddr_t);
void armv7_tlb_flushI_SE(vaddr_t);
void armv7_tlb_flushD_SE(vaddr_t);
void armv7_cpu_sleep(int);
void armv7_drain_writebuf(void);
void armv7_setup(char *string);
#endif /* CPU_ARMV7 */
#if defined(CPU_PJ4B)
void pj4b_cpu_sleep(int);
void pj4bv7_setup(char *string);
void pj4b_config(void);
void pj4b_io_coherency_barrier(vaddr_t, paddr_t, vsize_t);
void pj4b_dcache_cfu_inv_range(vaddr_t, vsize_t);
void pj4b_dcache_cfu_wb_range(vaddr_t, vsize_t);
void pj4b_dcache_cfu_wbinv_range(vaddr_t, vsize_t);
#endif /* CPU_PJ4B */
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
void arm11x6_idcache_wbinv_all (void);
void arm11x6_dcache_wbinv_all (void);
void arm11x6_icache_sync_all (void);
void arm11x6_flush_prefetchbuf (void);
void arm11x6_icache_sync_range (vaddr_t, vsize_t);
void arm11x6_idcache_wbinv_range (vaddr_t, vsize_t);
void arm11x6_setup (char *string);
void arm11x6_sleep (int); /* no ref. for errata */
#endif
#if defined(CPU_ARM1136)
void arm1136_sleep_rev0 (int); /* for errata 336501 */
#endif
#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_FA526) || defined(CPU_XSCALE) || defined(CPU_SHEEVA)
void armv4_tlb_flushID (void);
void armv4_tlb_flushI (void);
void armv4_tlb_flushD (void);
void armv4_tlb_flushD_SE (vaddr_t);
void armv4_drain_writebuf (void);
#endif
#if defined(CPU_IXP12X0)
void ixp12x0_drain_readbuf (void);
void ixp12x0_context_switch (u_int);
void ixp12x0_setup (char *);
#endif
#if defined(CPU_XSCALE)
void xscale_cpwait (void);
void xscale_cpu_sleep (int);
u_int xscale_control (u_int, u_int);
void xscale_setttb (u_int, bool);
void xscale_tlb_flushID_SE (vaddr_t);
void xscale_cache_flushID (void);
void xscale_cache_flushI (void);
void xscale_cache_flushD (void);
void xscale_cache_flushD_SE (vaddr_t);
void xscale_cache_cleanID (void);
void xscale_cache_cleanD (void);
void xscale_cache_cleanD_E (u_int);
void xscale_cache_clean_minidata (void);
void xscale_cache_purgeID (void);
void xscale_cache_purgeID_E (u_int);
void xscale_cache_purgeD (void);
void xscale_cache_purgeD_E (u_int);
void xscale_cache_syncI (void);
void xscale_cache_cleanID_rng (vaddr_t, vsize_t);
void xscale_cache_cleanD_rng (vaddr_t, vsize_t);
void xscale_cache_purgeID_rng (vaddr_t, vsize_t);
void xscale_cache_purgeD_rng (vaddr_t, vsize_t);
void xscale_cache_syncI_rng (vaddr_t, vsize_t);
void xscale_cache_flushD_rng (vaddr_t, vsize_t);
void xscale_context_switch (u_int);
void xscale_setup (char *);
#endif /* CPU_XSCALE */
#if defined(CPU_SHEEVA)
void sheeva_dcache_wbinv_range (vaddr_t, vsize_t);
void sheeva_dcache_inv_range (vaddr_t, vsize_t);
void sheeva_dcache_wb_range (vaddr_t, vsize_t);
void sheeva_idcache_wbinv_range (vaddr_t, vsize_t);
void sheeva_setup(char *);
void sheeva_cpu_sleep(int);
void sheeva_sdcache_inv_range(vaddr_t, paddr_t, vsize_t);
void sheeva_sdcache_wb_range(vaddr_t, paddr_t, vsize_t);
void sheeva_sdcache_wbinv_range(vaddr_t, paddr_t, vsize_t);
void sheeva_sdcache_wbinv_all(void);
#endif
#endif /* _KERNEL */
#endif /* _ARM_CPUFUNC_PROTO_H_ */

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sys/arch/arm/include/db_machdep.h
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@ -1,141 +0,0 @@
/* $NetBSD: db_machdep.h,v 1.22 2014/09/13 18:08:38 matt Exp $ */
/*
* Copyright (c) 1996 Scott K Stevens
*
* Mach Operating System
* Copyright (c) 1991,1990 Carnegie Mellon University
* All Rights Reserved.
*
* Permission to use, copy, modify and distribute this software and its
* documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie Mellon
* the rights to redistribute these changes.
*/
#ifndef _ARM_DB_MACHDEP_H_
#define _ARM_DB_MACHDEP_H_
/*
* Machine-dependent defines for new kernel debugger.
*/
#include <sys/types.h>
#include <uvm/uvm_extern.h>
#include <arm/armreg.h>
#include <machine/frame.h>
#include <machine/trap.h>
/* end of mangling */
typedef vaddr_t db_addr_t; /* address - unsigned */
#define DDB_EXPR_FMT "l" /* expression is long */
typedef long db_expr_t; /* expression - signed */
typedef trapframe_t db_regs_t;
#ifndef MULTIPROCESSOR
extern db_regs_t ddb_regs; /* register state */
#define DDB_REGS (&ddb_regs)
#else
extern db_regs_t *ddb_regp;
#define DDB_REGS (ddb_regp)
#define ddb_regs (*ddb_regp)
#endif
#ifdef __PROG26
#define PC_REGS(regs) ((regs)->tf_r15 & R15_PC)
#define PC_ADVANCE(regs) ((regs)->tf_r15 += BKPT_SIZE)
#else
#define PC_REGS(regs) ((regs)->tf_pc)
#define PC_ADVANCE(r) ((r)->tf_r15 += BKPT_SIZE)
#endif
#define BKPT_ADDR(addr) (addr) /* breakpoint address */
#if defined(DDB)
#define BKPT_INST (KERNEL_BREAKPOINT) /* breakpoint instruction */
#else
/* breakpoint instruction if we use KGDB, this is used in db_set_temp_breakpoint() */
#define BKPT_INST (GDB5_BREAKPOINT)
#endif
#define BKPT_SIZE (INSN_SIZE) /* size of breakpoint inst */
#define BKPT_SET(inst, addr) (BKPT_INST)
/*#define FIXUP_PC_AFTER_BREAK(regs) ((regs)->tf_pc -= BKPT_SIZE)*/
#define T_FAULT (0)
#define T_BREAKPOINT (1)
#define IS_BREAKPOINT_TRAP(type, code) ((type) == T_BREAKPOINT)
#define IS_WATCHPOINT_TRAP(type, code) (0)
#define inst_trap_return(ins) (0)
/* ldmxx reg, {..., pc}
01800000 stack mode
000f0000 register
0000ffff register list */
/* mov pc, reg
0000000f register */
#define inst_return(ins) (((ins) & 0x0e108000) == 0x08108000 || \
((ins) & 0x0ff0fff0) == 0x01a0f000)
/* bl ...
00ffffff offset>>2 */
#define inst_call(ins) (((ins) & 0x0f000000) == 0x0b000000)
/* b ...
00ffffff offset>>2 */
/* ldr pc, [pc, reg, lsl #2]
0000000f register */
#define inst_branch(ins) (((ins) & 0x0f000000) == 0x0a000000 || \
((ins) & 0x0fdffff0) == 0x079ff100 || \
((ins) & 0x0ff0f000) == 0x0590f000)
#define inst_load(ins) (0)
#define inst_store(ins) (0)
#define inst_unconditional_flow_transfer(ins) \
(__SHIFTOUT((ins), INSN_COND_MASK) == INSN_COND_AL \
&& (inst_branch(ins) || inst_call(ins) || inst_return(ins)))
#define getreg_val (0)
#define next_instr_address(pc, bd) ((bd) ? (pc) : ((pc) + INSN_SIZE))
#define DB_MACHINE_COMMANDS
#define SOFTWARE_SSTEP
u_int branch_taken(u_int insn, u_int pc, db_regs_t *db_regs);
int kdb_trap(int, db_regs_t *);
void db_machine_init(void);
int db_validate_address(vaddr_t addr);
#define DB_ELF_SYMBOLS
#define DB_ELFSIZE 32
/*
* kgdb
*/
typedef register_t kgdb_reg_t;
#define KGDB_NUMREGS (16 + 8*3 + 2) /* r0..r15, f0..f7, fps, cpsr
* fp-registers are 12 bytes wide */
#define KGDB_REGNUM_R0 0
#define KGDB_REGNUM_SPSR 16 + 8*3 + 1
#define KGDB_BUFLEN 1024
/*
* MP stuff
*/
extern volatile struct cpu_info *db_onproc;
extern volatile struct cpu_info *db_newcpu;
#endif /* _ARM_DB_MACHDEP_H_ */

102
sys/arch/arm/include/disklabel.h
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@ -1,102 +0,0 @@
/* $NetBSD: disklabel.h,v 1.12 2013/05/27 07:37:20 msaitoh Exp $ */
/*
* Copyright (c) 1994 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* disklabel.h
*
* machine specific disk label info
*
* Created : 04/10/94
*/
#ifndef _ARM_DISKLABEL_H_
#define _ARM_DISKLABEL_H_
#ifndef LABELUSESMBR
#define LABELUSESMBR 1 /* use MBR partitionning */
#endif
#define LABELSECTOR 1 /* sector containing label */
#define LABELOFFSET 0 /* offset of label in sector */
#define MAXPARTITIONS 16 /* number of partitions */
#define OLDMAXPARTITIONS 8 /* old number of partitions */
#ifndef RAW_PART
#define RAW_PART 2 /* raw partition: XX?c */
#endif
/*
* We use the highest bit of the minor number for the partition number.
* This maintains backward compatibility with device nodes created before
* MAXPARTITIONS was increased.
*/
#define __ARM_MAXDISKS ((1 << 20) / MAXPARTITIONS)
#define DISKUNIT(dev) ((minor(dev) / OLDMAXPARTITIONS) % __ARM_MAXDISKS)
#define DISKPART(dev) ((minor(dev) % OLDMAXPARTITIONS) + \
((minor(dev) / (__ARM_MAXDISKS * OLDMAXPARTITIONS)) * OLDMAXPARTITIONS))
#define DISKMINOR(unit, part) \
(((unit) * OLDMAXPARTITIONS) + ((part) % OLDMAXPARTITIONS) + \
((part) / OLDMAXPARTITIONS) * (__ARM_MAXDISKS * OLDMAXPARTITIONS))
#if HAVE_NBTOOL_CONFIG_H
#include <nbinclude/sys/dkbad.h>
#include <nbinclude/sys/disklabel_acorn.h>
#include <nbinclude/sys/bootblock.h>
#else
#include <sys/dkbad.h>
#include <sys/disklabel_acorn.h>
#include <sys/bootblock.h>
#endif /* HAVE_NBTOOL_CONFIG_H */
struct cpu_disklabel {
struct mbr_partition mbrparts[MBR_PART_COUNT];
#define __HAVE_DISKLABEL_DKBAD
struct dkbad bad;
};
#ifdef _KERNEL
struct buf;
struct disklabel;
/* for readdisklabel. rv != 0 -> matches, msg == NULL -> success */
int mbr_label_read(dev_t, void (*)(struct buf *), struct disklabel *,
struct cpu_disklabel *, const char **, int *, int *);
/* for writedisklabel. rv == 0 -> dosen't match, rv > 0 -> success */
int mbr_label_locate(dev_t, void (*)(struct buf *),
struct disklabel *, struct cpu_disklabel *, int *, int *);
#endif /* _KERNEL */
#endif /* _ARM_DISKLABEL_H_ */

133
sys/arch/arm/include/ehabi.h
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@ -1,133 +0,0 @@
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* $NetBSD: ehabi.h,v 1.1 2013/08/12 23:22:12 matt Exp $ */
#ifndef _ARM_EHABI_H_
#define _ARM_EHABI_H_
#if defined(_KERNEL) || defined(_STANDALONE)
#include <sys/types.h>
#else
#include <inttypes.h>
#endif
typedef enum {
_URC_OK = 0, /* operation complete */
_URC_FOREIGN_EXCEPTION_CAUGHT = 1,
_URC_HANDLER_FOUND = 6,
_URC_INSTALL_CONTEXT = 7,
_URC_CONTINUE_UNWIND = 8,
_URC_FAILURE = 9, /* unspecified failure */
} _Unwind_Reason_Code;
typedef enum {
_UVRSC_CORE = 0, /* integer register */
_UVRSC_VFP = 1, /* vfp */
_UVRSC_WMMXD = 3, /* Intel WMMX data register */
_UVRSC_WMMXC = 4 /* Intel WMMX control register */
} _Unwind_VRS_RegClass;
typedef enum {
_UVRSD_UINT32 = 0,
_UVRSD_VFPX = 1,
_UVRSD_UINT64 = 3,
_UVRSD_FLOAT = 4,
_UVRSD_DOUBLE = 5
} _Unwind_VRS_DataRepresentation;
typedef enum {
_UVRSR_OK = 0,
_UVRSR_NOT_IMPLEMENTED = 1,
_UVRSR_FAILED = 2
} _Unwind_VRS_Result;
typedef uint32_t _Unwind_State;
static const _Unwind_State _US_VIRTUAL_UNWIND_FRAME = 0;
static const _Unwind_State _US_UNWIND_FRAME_STARTING = 1;
static const _Unwind_State _US_UNWIND_FRAME_RESUME = 2;
typedef struct _Unwind_Control_Block _Unwind_Control_Block;
typedef struct _Unwind_Context _Unwind_Context;
typedef uint32_t _Unwind_EHT_Header;
struct _Unwind_Control_Block {
char exception_class[8];
void (*exception_cleanup)(_Unwind_Reason_Code, _Unwind_Control_Block *);
/* Unwinder cache, private fields for the unwinder's use */
struct {
uint32_t reserved1;
uint32_t reserved2;
uint32_t reserved3;
uint32_t reserved4;
uint32_t reserved5;
/* init reserved1 to 0, then don't touch */
} unwinder_cache;
/* Propagation barrier cache (valid after phase 1): */
struct {
uint32_t sp;
uint32_t bitpattern[5];
} barrier_cache;
/* Cleanup cache (preserved over cleanup): */
struct {
uint32_t bitpattern[4];
} cleanup_cache;
/* Pr cache (for pr's benefit): */
struct {
uint32_t fnstart; /* function start address */
_Unwind_EHT_Header *ehtp; /* ptr to EHT entry header word */
uint32_t additional; /* additional data */
uint32_t reserved1;
} pr_cache;
uint64_t : 0; /* Force alignment of next item to 8-byte boundary */
};
__BEGIN_DECLS
/* Unwinding functions */
void _Unwind_Resume(_Unwind_Control_Block *);
void _Unwind_Complete(_Unwind_Control_Block *);
void _Unwind_DeleteException(_Unwind_Control_Block *);
_Unwind_Reason_Code _Unwind_RaiseException(_Unwind_Control_Block *);
_Unwind_VRS_Result _Unwind_VRS_Set(_Unwind_Context *, _Unwind_VRS_RegClass,
uint32_t, _Unwind_VRS_DataRepresentation, void *);
_Unwind_VRS_Result _Unwind_VRS_Get(_Unwind_Context *, _Unwind_VRS_RegClass,
uint32_t, _Unwind_VRS_DataRepresentation, void *);
_Unwind_VRS_Result _Unwind_VRS_Pop(_Unwind_Context *, _Unwind_VRS_RegClass,
uint32_t, _Unwind_VRS_DataRepresentation);
_Unwind_Reason_Code __aeabi_unwind_cpp_pr0(_Unwind_State,
_Unwind_Control_Block *, _Unwind_Context *);
_Unwind_Reason_Code __aeabi_unwind_cpp_pr1(_Unwind_State ,
_Unwind_Control_Block *, _Unwind_Context *);
_Unwind_Reason_Code __aeabi_unwind_cpp_pr2(_Unwind_State ,
_Unwind_Control_Block *, _Unwind_Context *);
__END_DECLS
#endif /* _ARM_EHABI_H_ */

160
sys/arch/arm/include/elf_machdep.h
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@ -1,160 +0,0 @@
/* $NetBSD: elf_machdep.h,v 1.17 2014/02/25 19:20:09 matt Exp $ */
#ifndef _ARM_ELF_MACHDEP_H_
#define _ARM_ELF_MACHDEP_H_
#if defined(__ARMEB__)
#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB
#else
#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB
#endif
#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */
#define ELF64_MACHDEP_ID_CASES \
/* no 64-bit ELF machine types supported */
/* Processor specific flags for the ELF header e_flags field. */
#define EF_ARM_RELEXEC 0x00000001
#define EF_ARM_HASENTRY 0x00000002
#define EF_ARM_INTERWORK 0x00000004 /* GNU binutils 000413 */
#define EF_ARM_SYMSARESORTED 0x00000004 /* ARM ELF A08 */
#define EF_ARM_APCS_26 0x00000008 /* GNU binutils 000413 */
#define EF_ARM_DYNSYMSUSESEGIDX 0x00000008 /* ARM ELF B01 */
#define EF_ARM_APCS_FLOAT 0x00000010 /* GNU binutils 000413 */
#define EF_ARM_MAPSYMSFIRST 0x00000010 /* ARM ELF B01 */
#define EF_ARM_PIC 0x00000020
#define EF_ARM_ALIGN8 0x00000040 /* 8-bit structure alignment. */
#define EF_ARM_NEW_ABI 0x00000080
#define EF_ARM_OLD_ABI 0x00000100
#define EF_ARM_SOFT_FLOAT 0x00000200
#define EF_ARM_BE8 0x00800000
#define EF_ARM_EABIMASK 0xff000000
#define EF_ARM_EABI_VER1 0x01000000
#define EF_ARM_EABI_VER2 0x02000000
#define EF_ARM_EABI_VER3 0x03000000
#define EF_ARM_EABI_VER4 0x04000000
#define EF_ARM_EABI_VER5 0x05000000
#define ELF32_MACHDEP_ID_CASES \
case EM_ARM: \
break;
#define ELF32_MACHDEP_ID EM_ARM
#define ARCH_ELFSIZE 32 /* MD native binary size */
/* Processor specific relocation types */
#define R_ARM_NONE 0
#define R_ARM_PC24 1
#define R_ARM_ABS32 2
#define R_ARM_REL32 3
#define R_ARM_PC13 4
#define R_ARM_ABS16 5
#define R_ARM_ABS12 6
#define R_ARM_THM_ABS5 7
#define R_ARM_ABS8 8
#define R_ARM_SBREL32 9
#define R_ARM_THM_PC22 10
#define R_ARM_THM_PC8 11
#define R_ARM_AMP_VCALL9 12
#define R_ARM_SWI24 13
#define R_ARM_THM_SWI8 14
#define R_ARM_XPC25 15
#define R_ARM_THM_XPC22 16
/* TLS relocations */
#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */
#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */
#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */
/* 20-31 are reserved for ARM Linux. */
#define R_ARM_COPY 20
#define R_ARM_GLOB_DAT 21
#define R_ARM_JUMP_SLOT 22
#define R_ARM_RELATIVE 23
#define R_ARM_GOTOFF 24
#define R_ARM_GOTPC 25
#define R_ARM_GOT32 26
#define R_ARM_PLT32 27
#define R_ARM_CALL 28
#define R_ARM_JUMP24 29
#define R_ARM_THM_JUMP24 30
#define R_ARM_BASE_ABS 31
#define R_ARM_ALU_PCREL_7_0 32
#define R_ARM_ALU_PCREL_15_8 33
#define R_ARM_ALU_PCREL_23_15 34
#define R_ARM_ALU_SBREL_11_0 35
#define R_ARM_ALU_SBREL_19_12 36
#define R_ARM_ALU_SBREL_27_20 37 // depcreated
#define R_ARM_TARGET1 38
#define R_ARM_SBREL31 39 // deprecated
#define R_ARM_V4BX 40
#define R_ARM_TARGET2 41
#define R_ARM_PREL31 42
#define R_ARM_MOVW_ABS_NC 43
#define R_ARM_MOVT_ABS 44
#define R_ARM_MOVW_PREL_NC 45
#define R_ARM_MOVT_PREL 46
#define R_ARM_THM_MOVW_ABS_NC 47
#define R_ARM_THM_MOVT_ABS 48
#define R_ARM_THM_MOVW_PREL_NC 49
#define R_ARM_THM_MOVT_PREL 50
/* 96-111 are reserved to G++. */
#define R_ARM_GNU_VTENTRY 100
#define R_ARM_GNU_VTINHERIT 101
#define R_ARM_THM_PC11 102
#define R_ARM_THM_PC9 103
/* More TLS relocations */
#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic */
#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic */
#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS */
#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of */
#define R_ARM_TLS_LE32 108
#define R_ARM_TLS_LDO12 109
#define R_ARM_TLS_LE12 110
#define R_ARM_TLS_IE12GP 111
/* 112-127 are reserved for private experiments. */
#define R_ARM_RXPC25 249
#define R_ARM_RSBREL32 250
#define R_ARM_THM_RPC22 251
#define R_ARM_RREL32 252
#define R_ARM_RABS32 253
#define R_ARM_RPC24 254
#define R_ARM_RBASE 255
#define R_TYPE(name) __CONCAT(R_ARM_,name)
/* Processor specific program header flags */
#define PF_ARM_SB 0x10000000
#define PF_ARM_PI 0x20000000
#define PF_ARM_ENTRY 0x80000000
/* Processor specific program header types */
#define PT_ARM_EXIDX (PT_LOPROC + 1)
/* Processor specific section header flags */
#define SHF_ENTRYSECT 0x10000000
#define SHF_COMDEF 0x80000000
/* Processor specific symbol types */
#define STT_ARM_TFUNC STT_LOPROC
#ifdef _KERNEL
#ifdef ELFSIZE
#define ELF_MD_PROBE_FUNC ELFNAME2(arm_netbsd,probe)
#define ELF_MD_COREDUMP_SETUP ELFNAME2(arm_netbsd,coredump_setup)
#endif
struct exec_package;
int arm_netbsd_elf32_probe(struct lwp *, struct exec_package *, void *, char *,
vaddr_t *);
void arm_netbsd_elf32_coredump_setup(struct lwp *, void *);
#endif
#endif /* _ARM_ELF_MACHDEP_H_ */

3
sys/arch/arm/include/endian.h
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@ -1,3 +0,0 @@
/* $NetBSD: endian.h,v 1.3 2001/06/23 12:20:27 bjh21 Exp $ */
#include <sys/endian.h>

8
sys/arch/arm/include/endian_machdep.h
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@ -1,8 +0,0 @@
/* $NetBSD: endian_machdep.h,v 1.9 2014/01/29 01:03:13 matt Exp $ */
/* __ARMEB__ or __AARCH64EB__ is predefined when building big-endian ARM. */
#if defined(__ARMEB__) || defined(__AARCH64EB__)
#define _BYTE_ORDER _BIG_ENDIAN
#else
#define _BYTE_ORDER _LITTLE_ENDIAN
#endif

45
sys/arch/arm/include/fenv.h
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@ -1,45 +0,0 @@
/* $NetBSD: fenv.h,v 1.3 2015/03/17 12:20:02 joerg Exp $ */
/*
* Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995
* Public domain.
*/
#ifndef _ARM_FENV_H_
#define _ARM_FENV_H_
#include <sys/cdefs.h>
#ifdef __ARM_PCS_AAPCS64
/* AArch64 split FPSCR into two registers FPCR and FPSR */
typedef struct {
unsigned int __fpcr;
unsigned int __fpsr;
} fenv_t;
#else
typedef int fenv_t; /* FPSCR */
#endif
typedef int fexcept_t;
#define FE_INVALID 0x01 /* invalid operation exception */
#define FE_DIVBYZERO 0x02 /* divide-by-zero exception */
#define FE_OVERFLOW 0x04 /* overflow exception */
#define FE_UNDERFLOW 0x08 /* underflow exception */
#define FE_INEXACT 0x10 /* imprecise (loss of precision; "inexact") */
#define FE_ALL_EXCEPT 0x1f
#define FE_TONEAREST 0 /* round to nearest representable number */
#define FE_UPWARD 1 /* round toward positive infinity */
#define FE_DOWNWARD 2 /* round toward negative infinity */
#define FE_TOWARDZERO 3 /* round to zero (truncate) */
__BEGIN_DECLS
/* Default floating-point environment */
extern const fenv_t __fe_dfl_env;
#define FE_DFL_ENV (&__fe_dfl_env)
__END_DECLS
#endif /* _ARM_FENV_H_ */

68
sys/arch/arm/include/fiq.h
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@ -1,68 +0,0 @@
/* $NetBSD: fiq.h,v 1.1 2001/12/20 01:20:23 thorpej Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_FIQ_H_
#define _ARM_FIQ_H_
#include <sys/queue.h>
struct fiqregs {
u_int fr_r8; /* FIQ mode r8 */
u_int fr_r9; /* FIQ mode r9 */
u_int fr_r10; /* FIQ mode r10 */
u_int fr_r11; /* FIQ mode r11 */
u_int fr_r12; /* FIQ mode r12 */
u_int fr_r13; /* FIQ mode r13 */
};
struct fiqhandler {
TAILQ_ENTRY(fiqhandler) fh_list;/* link in the FIQ handler stack */
void *fh_func; /* FIQ handler routine */
size_t fh_size; /* size of FIQ handler */
int fh_flags; /* flags; see below */
struct fiqregs *fh_regs; /* pointer to regs structure */
};
#define FH_CANPUSH 0x01 /* can push this handler out of the way */
int fiq_claim(struct fiqhandler *);
void fiq_release(struct fiqhandler *);
void fiq_getregs(struct fiqregs *);
void fiq_setregs(struct fiqregs *);
#endif /* _ARM_FIQ_H_ */

63
sys/arch/arm/include/float.h
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@ -1,63 +0,0 @@
/* $NetBSD: float.h,v 1.8 2014/01/29 01:10:36 matt Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_FLOAT_H_
#define _ARM_FLOAT_H_
#include <sys/cdefs.h>
#ifdef __ARM_PCS_AAPCS64
#define LDBL_MANT_DIG __LDBL_MANT_DIG__
#define LDBL_DIG __LDBL_DIG__
#define LDBL_MIN_EXP __LDBL_MIN_EXP__
#define LDBL_MIN_10_EXP __LDBL_MIN_10_EXP__
#define LDBL_MAX_EXP __LDBL_MAX_EXP__
#define LDBL_MAX_10_EXP __LDBL_MAX_10_EXP__
#define LDBL_EPSILON __LDBL_EPSILON__
#define LDBL_MIN __LDBL_MIN__
#define LDBL_MAX __LDBL_MAX__
#endif /* __ARM_PCS_AAPCS64 */
#include <sys/float_ieee754.h>
#if defined(__ARM_PCS_AAPCS64) \
&& ((!defined(_ANSI_SOURCE) && !defined(_POSIX_C_SOURCE) \
&& !defined(_XOPEN_SOURCE)) \
|| (__STDC_VERSION__ - 0) >= 199901L \
|| (_POSIX_C_SOURCE - 0) >= 200112L \
|| ((_XOPEN_SOURCE - 0) >= 600) \
|| defined(_ISOC99_SOURCE) || defined(_NETBSD_SOURCE))
#define DECIMAL_DIG __DECIMAL_DIG__
#endif /* __ARM_PCS_AAPCS64 && ... */
#endif /* !_ARM_FLOAT_H_ */

119
sys/arch/arm/include/frame.h
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@ -1,119 +0,0 @@
/* $NetBSD: frame.h,v 1.18 2013/08/18 05:07:19 matt Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* arm/frame.h - Stack frames structures common to arm26 and arm32
*/
#ifndef _ARM_FRAME_H_
#define _ARM_FRAME_H_
#ifndef _LOCORE
#include <sys/signal.h>
#include <sys/ucontext.h>
/*
* Trap frame. Pushed onto the kernel stack on a trap (synchronous exception).
*/
typedef struct trapframe {
register_t tf_spsr; /* Zero on arm26 */
register_t tf_fill; /* fill here so r0 will be dword aligned */
register_t tf_r0;
register_t tf_r1;
register_t tf_r2;
register_t tf_r3;
register_t tf_r4;
register_t tf_r5;
register_t tf_r6;
register_t tf_r7;
register_t tf_r8;
register_t tf_r9;
register_t tf_r10;
register_t tf_r11;
register_t tf_r12;
register_t tf_usr_sp;
register_t tf_usr_lr;
register_t tf_svc_sp; /* Not used on arm26 */
register_t tf_svc_lr; /* Not used on arm26 */
register_t tf_pc;
} trapframe_t;
/* Register numbers */
#define tf_ip tf_r12
#define tf_r13 tf_usr_sp
#define tf_r14 tf_usr_lr
#define tf_r15 tf_pc
#ifdef __PROG32
#define TRAP_USERMODE(tf) (((tf)->tf_spsr & PSR_MODE) == PSR_USR32_MODE)
#elif defined(__PROG26)
#define TRAP_USERMODE(tf) (((tf)->tf_r15 & R15_MODE) == R15_MODE_USR)
#endif
/*
* Signal frame. Pushed onto user stack before calling sigcode.
*/
#if defined(COMPAT_16) || defined(__minix)
struct sigframe_sigcontext {
#if defined(__minix)
struct sigcontext *sf_scp; /* Let sigreturn find sigcontext */
#endif /* defined(__minix) */
struct sigcontext sf_sc;
};
#endif
/* the pointers are use in the trampoline code to locate the ucontext */
struct sigframe_siginfo {
siginfo_t sf_si; /* actual saved siginfo */
ucontext_t sf_uc; /* actual saved ucontext */
};
#ifdef _KERNEL
__BEGIN_DECLS
void sendsig_sigcontext(const ksiginfo_t *, const sigset_t *);
void *getframe(struct lwp *, int, int *);
__END_DECLS
#define lwp_trapframe(l) ((l)->l_md.md_tf)
#define lwp_settrapframe(l, tf) ((l)->l_md.md_tf = (tf))
#endif
#endif /* _LOCORE */
#endif /* _ARM_FRAME_H_ */
/* End of frame.h */

4
sys/arch/arm/include/ieee.h
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@ -1,4 +0,0 @@
/* $NetBSD: ieee.h,v 1.11 2014/01/31 19:38:06 matt Exp $ */
#include <arm/math.h> /* for #define __HAVE_LONG_DOUBLE 128 */
#include <sys/ieee754.h>

44
sys/arch/arm/include/ieeefp.h
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@ -1,44 +0,0 @@
/* $NetBSD: ieeefp.h,v 1.3 2013/04/23 05:42:23 matt Exp $ */
/*
* Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995
* Public domain.
*/
#ifndef _ARM_IEEEFP_H_
#define _ARM_IEEEFP_H_
#include <sys/featuretest.h>
#if defined(_NETBSD_SOURCE) || defined(_ISOC99_SOURCE)
#include <arm/fenv.h>
#if !defined(_ISOC99_SOURCE)
/* Exception type (used by fpsetmask() et al.) */
typedef int fp_except;
/* Bit defines for fp_except */
#define FP_X_INV FE_INVALID /* invalid operation exception */
#define FP_X_DZ FE_DIVBYZERO /* divide-by-zero exception */
#define FP_X_OFL FE_OVERFLOW /* overflow exception */
#define FP_X_UFL FE_UNDERFLOW /* underflow exception */
#define FP_X_IMP FE_INEXACT /* imprecise (prec. loss; "inexact") */
/* Rounding modes */
typedef enum {
FP_RN=FE_TONEAREST, /* round to nearest representable number */
FP_RP=FE_UPWARD, /* round toward positive infinity */
FP_RM=FE_DOWNWARD, /* round toward negative infinity */
FP_RZ=FE_TOWARDZERO /* round to zero (truncate) */
} fp_rnd;
#endif /* !_ISOC99_SOURCE */
#endif /* _NETBSD_SOURCE || _ISOC99_SOURCE */
#endif /* _ARM_IEEEFP_H_ */

60
sys/arch/arm/include/int_const.h
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@ -1,60 +0,0 @@
/* $NetBSD: int_const.h,v 1.4 2014/07/25 21:43:13 joerg Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_INT_CONST_H_
#define _ARM_INT_CONST_H_
#ifdef __INTMAX_C_SUFFIX__
#include <sys/common_int_const.h>
#else
/*
* 7.18.4 Macros for integer constants
*/
/* 7.18.4.1 Macros for minimum-width integer constants */
#define INT8_C(c) c
#define INT16_C(c) c
#define INT32_C(c) c
#define INT64_C(c) c ## LL
#define UINT8_C(c) c
#define UINT16_C(c) c
#define UINT32_C(c) c ## U
#define UINT64_C(c) c ## ULL
/* 7.18.4.2 Macros for greatest-width integer constants */
#define INTMAX_C(c) c ## LL
#define UINTMAX_C(c) c ## ULL
#endif
#endif /* !_ARM_INT_CONST_H_ */

216
sys/arch/arm/include/int_fmtio.h
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@ -1,216 +0,0 @@
/* $NetBSD: int_fmtio.h,v 1.9 2014/08/13 19:48:17 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_INT_FMTIO_H_
#define _ARM_INT_FMTIO_H_
#ifdef __INTPTR_FMTd__
#include <sys/common_int_fmtio.h>
#else
/*
* 7.8.1 Macros for format specifiers
*/
/* fprintf macros for signed integers */
#define PRId8 "d" /* int8_t */
#define PRId16 "d" /* int16_t */
#define PRId32 "d" /* int32_t */
#define PRId64 "lld" /* int64_t */
#define PRIdLEAST8 "d" /* int_least8_t */
#define PRIdLEAST16 "d" /* int_least16_t */
#define PRIdLEAST32 "d" /* int_least32_t */
#define PRIdLEAST64 "lld" /* int_least64_t */
#define PRIdFAST8 "d" /* int_fast8_t */
#define PRIdFAST16 "d" /* int_fast16_t */
#define PRIdFAST32 "d" /* int_fast32_t */
#define PRIdFAST64 "lld" /* int_fast64_t */
#define PRIdMAX "lld" /* intmax_t */
#define PRIdPTR "ld" /* intptr_t */
#define PRIi8 "i" /* int8_t */
#define PRIi16 "i" /* int16_t */
#define PRIi32 "i" /* int32_t */
#define PRIi64 "lli" /* int64_t */
#define PRIiLEAST8 "i" /* int_least8_t */
#define PRIiLEAST16 "i" /* int_least16_t */
#define PRIiLEAST32 "i" /* int_least32_t */
#define PRIiLEAST64 "lli" /* int_least64_t */
#define PRIiFAST8 "i" /* int_fast8_t */
#define PRIiFAST16 "i" /* int_fast16_t */
#define PRIiFAST32 "i" /* int_fast32_t */
#define PRIiFAST64 "lli" /* int_fast64_t */
#define PRIiMAX "lli" /* intmax_t */
#define PRIiPTR "li" /* intptr_t */
/* fprintf macros for unsigned integers */
#define PRIo8 "o" /* uint8_t */
#define PRIo16 "o" /* uint16_t */
#define PRIo32 "o" /* uint32_t */
#define PRIo64 "llo" /* uint64_t */
#define PRIoLEAST8 "o" /* uint_least8_t */
#define PRIoLEAST16 "o" /* uint_least16_t */
#define PRIoLEAST32 "o" /* uint_least32_t */
#define PRIoLEAST64 "llo" /* uint_least64_t */
#define PRIoFAST8 "o" /* uint_fast8_t */
#define PRIoFAST16 "o" /* uint_fast16_t */
#define PRIoFAST32 "o" /* uint_fast32_t */
#define PRIoFAST64 "llo" /* uint_fast64_t */
#define PRIoMAX "llo" /* uintmax_t */
#define PRIoPTR "lo" /* uintptr_t */
#define PRIu8 "u" /* uint8_t */
#define PRIu16 "u" /* uint16_t */
#define PRIu32 "u" /* uint32_t */
#define PRIu64 "llu" /* uint64_t */
#define PRIuLEAST8 "u" /* uint_least8_t */
#define PRIuLEAST16 "u" /* uint_least16_t */
#define PRIuLEAST32 "u" /* uint_least32_t */
#define PRIuLEAST64 "llu" /* uint_least64_t */
#define PRIuFAST8 "u" /* uint_fast8_t */
#define PRIuFAST16 "u" /* uint_fast16_t */
#define PRIuFAST32 "u" /* uint_fast32_t */
#define PRIuFAST64 "llu" /* uint_fast64_t */
#define PRIuMAX "llu" /* uintmax_t */
#define PRIuPTR "lu" /* uintptr_t */
#define PRIx8 "x" /* uint8_t */
#define PRIx16 "x" /* uint16_t */
#define PRIx32 "x" /* uint32_t */
#define PRIx64 "llx" /* uint64_t */
#define PRIxLEAST8 "x" /* uint_least8_t */
#define PRIxLEAST16 "x" /* uint_least16_t */
#define PRIxLEAST32 "x" /* uint_least32_t */
#define PRIxLEAST64 "llx" /* uint_least64_t */
#define PRIxFAST8 "x" /* uint_fast8_t */
#define PRIxFAST16 "x" /* uint_fast16_t */
#define PRIxFAST32 "x" /* uint_fast32_t */
#define PRIxFAST64 "llx" /* uint_fast64_t */
#define PRIxMAX "llx" /* uintmax_t */
#define PRIxPTR "lx" /* uintptr_t */
#define PRIX8 "X" /* uint8_t */
#define PRIX16 "X" /* uint16_t */
#define PRIX32 "X" /* uint32_t */
#define PRIX64 "llX" /* uint64_t */
#define PRIXLEAST8 "X" /* uint_least8_t */
#define PRIXLEAST16 "X" /* uint_least16_t */
#define PRIXLEAST32 "X" /* uint_least32_t */
#define PRIXLEAST64 "llX" /* uint_least64_t */
#define PRIXFAST8 "X" /* uint_fast8_t */
#define PRIXFAST16 "X" /* uint_fast16_t */
#define PRIXFAST32 "X" /* uint_fast32_t */
#define PRIXFAST64 "llX" /* uint_fast64_t */
#define PRIXMAX "llX" /* uintmax_t */
#define PRIXPTR "lX" /* uintptr_t */
/* fscanf macros for signed integers */
#define SCNd8 "hhd" /* int8_t */
#define SCNd16 "hd" /* int16_t */
#define SCNd32 "d" /* int32_t */
#define SCNd64 "lld" /* int64_t */
#define SCNdLEAST8 "hhd" /* int_least8_t */
#define SCNdLEAST16 "hd" /* int_least16_t */
#define SCNdLEAST32 "d" /* int_least32_t */
#define SCNdLEAST64 "lld" /* int_least64_t */
#define SCNdFAST8 "d" /* int_fast8_t */
#define SCNdFAST16 "d" /* int_fast16_t */
#define SCNdFAST32 "d" /* int_fast32_t */
#define SCNdFAST64 "lld" /* int_fast64_t */
#define SCNdMAX "lld" /* intmax_t */
#define SCNdPTR "ld" /* intptr_t */
#define SCNi8 "hhi" /* int8_t */
#define SCNi16 "hi" /* int16_t */
#define SCNi32 "i" /* int32_t */
#define SCNi64 "lli" /* int64_t */
#define SCNiLEAST8 "hhi" /* int_least8_t */
#define SCNiLEAST16 "hi" /* int_least16_t */
#define SCNiLEAST32 "i" /* int_least32_t */
#define SCNiLEAST64 "lli" /* int_least64_t */
#define SCNiFAST8 "i" /* int_fast8_t */
#define SCNiFAST16 "i" /* int_fast16_t */
#define SCNiFAST32 "i" /* int_fast32_t */
#define SCNiFAST64 "lli" /* int_fast64_t */
#define SCNiMAX "lli" /* intmax_t */
#define SCNiPTR "li" /* intptr_t */
/* fscanf macros for unsigned integers */
#define SCNo8 "hho" /* uint8_t */
#define SCNo16 "ho" /* uint16_t */
#define SCNo32 "o" /* uint32_t */
#define SCNo64 "llo" /* uint64_t */
#define SCNoLEAST8 "hho" /* uint_least8_t */
#define SCNoLEAST16 "ho" /* uint_least16_t */
#define SCNoLEAST32 "o" /* uint_least32_t */
#define SCNoLEAST64 "llo" /* uint_least64_t */
#define SCNoFAST8 "o" /* uint_fast8_t */
#define SCNoFAST16 "o" /* uint_fast16_t */
#define SCNoFAST32 "o" /* uint_fast32_t */
#define SCNoFAST64 "llo" /* uint_fast64_t */
#define SCNoMAX "llo" /* uintmax_t */
#define SCNoPTR "lo" /* uintptr_t */
#define SCNu8 "hhu" /* uint8_t */
#define SCNu16 "hu" /* uint16_t */
#define SCNu32 "u" /* uint32_t */
#define SCNu64 "llu" /* uint64_t */
#define SCNuLEAST8 "hhu" /* uint_least8_t */
#define SCNuLEAST16 "hu" /* uint_least16_t */
#define SCNuLEAST32 "u" /* uint_least32_t */
#define SCNuLEAST64 "llu" /* uint_least64_t */
#define SCNuFAST8 "u" /* uint_fast8_t */
#define SCNuFAST16 "u" /* uint_fast16_t */
#define SCNuFAST32 "u" /* uint_fast32_t */
#define SCNuFAST64 "llu" /* uint_fast64_t */
#define SCNuMAX "llu" /* uintmax_t */
#define SCNuPTR "lu" /* uintptr_t */
#define SCNx8 "hhx" /* uint8_t */
#define SCNx16 "hx" /* uint16_t */
#define SCNx32 "x" /* uint32_t */
#define SCNx64 "llx" /* uint64_t */
#define SCNxLEAST8 "hhx" /* uint_least8_t */
#define SCNxLEAST16 "hx" /* uint_least16_t */
#define SCNxLEAST32 "x" /* uint_least32_t */
#define SCNxLEAST64 "llx" /* uint_least64_t */
#define SCNxFAST8 "x" /* uint_fast8_t */
#define SCNxFAST16 "x" /* uint_fast16_t */
#define SCNxFAST32 "x" /* uint_fast32_t */
#define SCNxFAST64 "llx" /* uint_fast64_t */
#define SCNxMAX "llx" /* uintmax_t */
#define SCNxPTR "lx" /* uintptr_t */
#endif /* !__INTPTR_FMTd__ */
#endif /* !_ARM_INT_FMTIO_H_ */

146
sys/arch/arm/include/int_limits.h
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@ -1,146 +0,0 @@
/* $NetBSD: int_limits.h,v 1.11 2014/07/25 21:43:13 joerg Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_INT_LIMITS_H_
#define _ARM_INT_LIMITS_H_
#ifdef __SIG_ATOMIC_MAX__
#include <sys/common_int_limits.h>
#else
/*
* 7.18.2 Limits of specified-width integer types
*/
/* 7.18.2.1 Limits of exact-width integer types */
/* minimum values of exact-width signed integer types */
#define INT8_MIN (-0x7f-1) /* int8_t */
#define INT16_MIN (-0x7fff-1) /* int16_t */
#define INT32_MIN (-0x7fffffff-1) /* int32_t */
#define INT64_MIN (-0x7fffffffffffffffLL-1) /* int64_t */
/* maximum values of exact-width signed integer types */
#define INT8_MAX 0x7f /* int8_t */
#define INT16_MAX 0x7fff /* int16_t */
#define INT32_MAX 0x7fffffff /* int32_t */
#define INT64_MAX 0x7fffffffffffffffLL /* int64_t */
/* maximum values of exact-width unsigned integer types */
#define UINT8_MAX 0xff /* uint8_t */
#define UINT16_MAX 0xffff /* uint16_t */
#define UINT32_MAX 0xffffffffU /* uint32_t */
#define UINT64_MAX 0xffffffffffffffffULL /* uint64_t */
/* 7.18.2.2 Limits of minimum-width integer types */
/* minimum values of minimum-width signed integer types */
#define INT_LEAST8_MIN (-0x7f-1) /* int_least8_t */
#define INT_LEAST16_MIN (-0x7fff-1) /* int_least16_t */
#define INT_LEAST32_MIN (-0x7fffffff-1) /* int_least32_t */
#define INT_LEAST64_MIN (-0x7fffffffffffffffLL-1) /* int_least64_t */
/* maximum values of minimum-width signed integer types */
#define INT_LEAST8_MAX 0x7f /* int_least8_t */
#define INT_LEAST16_MAX 0x7fff /* int_least16_t */
#define INT_LEAST32_MAX 0x7fffffff /* int_least32_t */
#define INT_LEAST64_MAX 0x7fffffffffffffffLL /* int_least64_t */
/* maximum values of minimum-width unsigned integer types */
#define UINT_LEAST8_MAX 0xff /* uint_least8_t */
#define UINT_LEAST16_MAX 0xffff /* uint_least16_t */
#define UINT_LEAST32_MAX 0xffffffffU /* uint_least32_t */
#define UINT_LEAST64_MAX 0xffffffffffffffffULL /* uint_least64_t */
/* 7.18.2.3 Limits of fastest minimum-width integer types */
/* minimum values of fastest minimum-width signed integer types */
#define INT_FAST8_MIN (-0x7fffffff-1) /* int_fast8_t */
#define INT_FAST16_MIN (-0x7fffffff-1) /* int_fast16_t */
#define INT_FAST32_MIN (-0x7fffffff-1) /* int_fast32_t */
#define INT_FAST64_MIN (-0x7fffffffffffffffLL-1) /* int_fast64_t */
/* maximum values of fastest minimum-width signed integer types */
#define INT_FAST8_MAX 0x7fffffff /* int_fast8_t */
#define INT_FAST16_MAX 0x7fffffff /* int_fast16_t */
#define INT_FAST32_MAX 0x7fffffff /* int_fast32_t */
#define INT_FAST64_MAX 0x7fffffffffffffffLL /* int_fast64_t */
/* maximum values of fastest minimum-width unsigned integer types */
#define UINT_FAST8_MAX 0xffffffffU /* uint_fast8_t */
#define UINT_FAST16_MAX 0xffffffffU /* uint_fast16_t */
#define UINT_FAST32_MAX 0xffffffffU /* uint_fast32_t */
#define UINT_FAST64_MAX 0xffffffffffffffffULL /* uint_fast64_t */
/* 7.18.2.4 Limits of integer types capable of holding object pointers */
#ifdef _LP64
#define INTPTR_MIN (-0x7fffffffffffffffL-1) /* intptr_t */
#define INTPTR_MAX 0x7fffffffffffffffL /* intptr_t */
#define UINTPTR_MAX 0xffffffffffffffffUL /* uintptr_t */
#else
#define INTPTR_MIN (-0x7fffffffL-1) /* intptr_t */
#define INTPTR_MAX 0x7fffffffL /* intptr_t */
#define UINTPTR_MAX 0xffffffffUL /* uintptr_t */
#endif
/* 7.18.2.5 Limits of greatest-width integer types */
#define INTMAX_MIN (-0x7fffffffffffffffLL-1) /* intmax_t */
#define INTMAX_MAX 0x7fffffffffffffffLL /* intmax_t */
#define UINTMAX_MAX 0xffffffffffffffffULL /* uintmax_t */
/*
* 7.18.3 Limits of other integer types
*/
/* limits of ptrdiff_t */
#ifdef _LP64
#define PTRDIFF_MIN (-0x7fffffffffffffffL-1) /* ptrdiff_t */
#define PTRDIFF_MAX 0x7fffffffffffffffL /* ptrdiff_t */
#else
#define PTRDIFF_MIN (-0x7fffffffL-1) /* ptrdiff_t */
#define PTRDIFF_MAX 0x7fffffffL /* ptrdiff_t */
#endif
/* limits of sig_atomic_t */
#define SIG_ATOMIC_MIN (-0x7fffffff-1) /* sig_atomic_t */
#define SIG_ATOMIC_MAX 0x7fffffff /* sig_atomic_t */
/* limit of size_t */
#ifdef _LP64
#define SIZE_MAX 0xffffffffffffffffUL /* size_t */
#else
#define SIZE_MAX 0xffffffffUL /* size_t */
#endif
#endif
#endif /* !_ARM_INT_LIMITS_H_ */

127
sys/arch/arm/include/int_mwgwtypes.h
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@ -1,127 +0,0 @@
/* $NetBSD: int_mwgwtypes.h,v 1.7 2014/07/25 21:43:13 joerg Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_INT_MWGWTYPES_H_
#define _ARM_INT_MWGWTYPES_H_
#ifdef __UINT_FAST64_TYPE__
#include <sys/common_int_mwgwtypes.h>
#else
/*
* 7.18.1 Integer types
*/
/* 7.18.1.2 Minimum-width integer types */
#ifndef __INT_LEAST8_TYPE__
# define __INT_LEAST8_TYPE__ signed char
#endif
#ifndef __UINT_LEAST8_TYPE__
# define __UINT_LEAST8_TYPE__ unsigned char
#endif
#ifndef __INT_LEAST16_TYPE__
# define __INT_LEAST16_TYPE__ short int
#endif
#ifndef __UINT_LEAST16_TYPE__
# define __UINT_LEAST16_TYPE__ short unsigned int
#endif
#ifndef __INT_LEAST32_TYPE__
# define __INT_LEAST32_TYPE__ int
#endif
#ifndef __UINT_LEAST32_TYPE__
# define __UINT_LEAST32_TYPE__ unsigned int
#endif
#ifndef __INT_LEAST64_TYPE__
# define __INT_LEAST64_TYPE__ long long int
#endif
#ifndef __UINT_LEAST64_TYPE__
# define __UINT_LEAST64_TYPE__ long long unsigned int
#endif
typedef __INT_LEAST8_TYPE__ int_least8_t;
typedef __UINT_LEAST8_TYPE__ uint_least8_t;
typedef __INT_LEAST16_TYPE__ int_least16_t;
typedef __UINT_LEAST16_TYPE__ uint_least16_t;
typedef __INT_LEAST32_TYPE__ int_least32_t;
typedef __UINT_LEAST32_TYPE__ uint_least32_t;
typedef __INT_LEAST64_TYPE__ int_least64_t;
typedef __UINT_LEAST64_TYPE__ uint_least64_t;
/* 7.18.1.3 Fastest minimum-width integer types */
#ifndef __INT_FAST8_TYPE__
# define __INT_FAST8_TYPE__ int
#endif
#ifndef __UINT_FAST8_TYPE__
# define __UINT_FAST8_TYPE__ unsigned int
#endif
#ifndef __INT_FAST16_TYPE__
# define __INT_FAST16_TYPE__ int
#endif
#ifndef __UINT_FAST16_TYPE__
# define __UINT_FAST16_TYPE__ unsigned int
#endif
#ifndef __INT_FAST32_TYPE__
# define __INT_FAST32_TYPE__ int
#endif
#ifndef __UINT_FAST32_TYPE__
# define __UINT_FAST32_TYPE__ unsigned int
#endif
#ifndef __INT_FAST64_TYPE__
# define __INT_FAST64_TYPE__ long long int
#endif
#ifndef __UINT_FAST64_TYPE__
# define __UINT_FAST64_TYPE__ long long unsigned int
#endif
typedef __INT_FAST8_TYPE__ int_fast8_t;
typedef __UINT_FAST8_TYPE__ uint_fast8_t;
typedef __INT_FAST16_TYPE__ int_fast16_t;
typedef __UINT_FAST16_TYPE__ uint_fast16_t;
typedef __INT_FAST32_TYPE__ int_fast32_t;
typedef __UINT_FAST32_TYPE__ uint_fast32_t;
typedef __INT_FAST64_TYPE__ int_fast64_t;
typedef __UINT_FAST64_TYPE__ uint_fast64_t;
/* 7.18.1.5 Greatest-width integer types */
#ifndef __INTMAX_TYPE__
# define __INTMAX_TYPE__ long long int
#endif
#ifndef __UINTMAX_TYPE__
# define __UINTMAX_TYPE__ unsigned __INTMAX_TYPE__
#endif
typedef __INTMAX_TYPE__ intmax_t;
typedef __UINTMAX_TYPE__ uintmax_t;
#endif
#endif /* !_ARM_INT_MWGWTYPES_H_ */

101
sys/arch/arm/include/int_types.h
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@ -1,101 +0,0 @@
/* $NetBSD: int_types.h,v 1.17 2014/07/25 21:43:13 joerg Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas of 3am Software Foundry.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_INT_TYPES_H_
#define _ARM_INT_TYPES_H_
#ifdef __UINTPTR_TYPE__
#include <sys/common_int_types.h>
#else
#include <sys/cdefs.h>
/*
* 7.18.1 Integer types
*/
/* 7.18.1.1 Exact-width integer types */
#ifndef __UINT8_TYPE__
# define __UINT8_TYPE__ unsigned char
#endif
#ifndef __INT8_TYPE__
# define __INT8_TYPE__ signed char
#endif
#ifndef __UINT16_TYPE__
# ifndef __INT16_TYPE__
# define __INT16_TYPE__ short int
# endif
# define __UINT16_TYPE__ unsigned __INT16_TYPE__
#endif
#ifndef __UINT32_TYPE__
# ifndef __INT32_TYPE__
# define __INT32_TYPE__ int
# endif
# define __UINT32_TYPE__ unsigned __INT32_TYPE__
#endif
#ifndef __UINT64_TYPE__
# ifndef __INT64_TYPE__
# define __INT64_TYPE__ long long int
# endif
# define __UINT64_TYPE__ unsigned __INT64_TYPE__
#endif
#ifdef __clang__
typedef signed __INT8_TYPE__ __int8_t;
#else
typedef __INT8_TYPE__ __int8_t;
#endif
typedef __UINT8_TYPE__ __uint8_t;
typedef __INT16_TYPE__ __int16_t;
typedef __UINT16_TYPE__ __uint16_t;
typedef __INT32_TYPE__ __int32_t;
typedef __UINT32_TYPE__ __uint32_t;
typedef __INT64_TYPE__ __int64_t;
typedef __UINT64_TYPE__ __uint64_t;
#if !defined(__minix)
#define __BIT_TYPES_DEFINED__
#endif /* !defined(__minix) */
/* 7.18.1.4 Integer types capable of holding object pointers */
#ifndef __UINTPTR_TYPE__
# ifndef __INTPTR_TYPE__
# define __INTPTR_TYPE__ long int
# endif
# define __UINTPTR_TYPE__ unsigned __INTPTR_TYPE__
#endif
typedef __INTPTR_TYPE__ __intptr_t;
typedef __UINTPTR_TYPE__ __uintptr_t;
#endif
#endif /* !_ARM_INT_TYPES_H_ */

146
sys/arch/arm/include/isa_machdep.h
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@ -1,146 +0,0 @@
/* $NetBSD: isa_machdep.h,v 1.11 2014/01/29 00:42:15 matt Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_ISA_MACHDEP_H_
#define _ARM_ISA_MACHDEP_H_
#include <sys/bus.h>
#include <dev/isa/isadmavar.h>
/*
* Types provided to machine-independent ISA code.
*/
struct arm32_isa_chipset {
struct isa_dma_state ic_dmastate;
};
typedef struct arm32_isa_chipset *isa_chipset_tag_t;
struct isabus_attach_args; /* XXX */
/*
* Functions provided to machine-independent ISA code.
*/
void isa_attach_hook(device_t, device_t,
struct isabus_attach_args *);
void isa_detach_hook(isa_chipset_tag_t, device_t);
const struct evcnt *isa_intr_evcnt(isa_chipset_tag_t ic, int irq);
void *isa_intr_establish(isa_chipset_tag_t ic, int irq, int type,
int level, int (*ih_fun)(void *), void *ih_arg);
void isa_intr_disestablish(isa_chipset_tag_t ic, void *handler);
#define isa_dmainit(ic, bst, dmat, d) \
_isa_dmainit(&(ic)->ic_dmastate, (bst), (dmat), (d))
#define isa_dmadestroy(ic) \
_isa_dmadestroy(&(ic)->ic_dmastate)
#define isa_dmacascade(ic, c) \
_isa_dmacascade(&(ic)->ic_dmastate, (c))
#define isa_dmamaxsize(ic, c) \
_isa_dmamaxsize(&(ic)->ic_dmastate, (c))
#define isa_dmamap_create(ic, c, s, f) \
_isa_dmamap_create(&(ic)->ic_dmastate, (c), (s), (f))
#define isa_dmamap_destroy(ic, c) \
_isa_dmamap_destroy(&(ic)->ic_dmastate, (c))
#define isa_dmastart(ic, c, a, n, p, f, bf) \
_isa_dmastart(&(ic)->ic_dmastate, (c), (a), (n), (p), (f), (bf))
#define isa_dmaabort(ic, c) \
_isa_dmaabort(&(ic)->ic_dmastate, (c))
#define isa_dmacount(ic, c) \
_isa_dmacount(&(ic)->ic_dmastate, (c))
#define isa_dmafinished(ic, c) \
_isa_dmafinished(&(ic)->ic_dmastate, (c))
#define isa_dmadone(ic, c) \
_isa_dmadone(&(ic)->ic_dmastate, (c))
#define isa_dmafreeze(ic) \
_isa_dmafreeze(&(ic)->ic_dmastate)
#define isa_dmathaw(ic) \
_isa_dmathaw(&(ic)->ic_dmastate)
#define isa_dmamem_alloc(ic, c, s, ap, f) \
_isa_dmamem_alloc(&(ic)->ic_dmastate, (c), (s), (ap), (f))
#define isa_dmamem_free(ic, c, a, s) \
_isa_dmamem_free(&(ic)->ic_dmastate, (c), (a), (s))
#define isa_dmamem_map(ic, c, a, s, kp, f) \
_isa_dmamem_map(&(ic)->ic_dmastate, (c), (a), (s), (kp), (f))
#define isa_dmamem_unmap(ic, c, k, s) \
_isa_dmamem_unmap(&(ic)->ic_dmastate, (c), (k), (s))
#define isa_dmamem_mmap(ic, c, a, s, o, p, f) \
_isa_dmamem_mmap(&(ic)->ic_dmastate, (c), (a), (s), (o), (p), (f))
#define isa_drq_alloc(ic, c) \
_isa_drq_alloc(&(ic)->ic_dmastate, c)
#define isa_drq_free(ic, c) \
_isa_drq_free(&(ic)->ic_dmastate, c)
#define isa_drq_isfree(ic, c) \
_isa_drq_isfree(&(ic)->ic_dmastate, (c))
#define isa_malloc(ic, c, s, p, f) \
_isa_malloc(&(ic)->ic_dmastate, (c), (s), (p), (f))
#define isa_free(a, p) \
_isa_free((a), (p))
#define isa_mappage(m, o, p) \
_isa_mappage((m), (o), (p))
/*
* ALL OF THE FOLLOWING ARE MACHINE-DEPENDENT, AND SHOULD NOT BE USED
* BY PORTABLE CODE.
*/
extern struct arm32_bus_dma_tag isa_bus_dma_tag;
/* bus space tags */
extern struct bus_space isa_io_bs_tag;
extern struct bus_space isa_mem_bs_tag;
/* ISA chipset */
extern struct arm32_isa_chipset isa_chipset_tag;
/* for pccons.c */
#define MONO_BASE 0x3B4
#define MONO_BUF 0x000B0000
#define CGA_BASE 0x3D4
#define CGA_BUF 0x000B8000
#define VGA_BUF 0xA0000
#define VGA_BUF_LEN (0xBFFFF - 0xA0000)
void isa_init(vaddr_t, vaddr_t);
void isa_io_init(vaddr_t, vaddr_t);
void isa_dma_init(void);
vaddr_t isa_io_data_vaddr(void);
vaddr_t isa_mem_data_vaddr(void);
int isa_intr_alloc(isa_chipset_tag_t ic, int mask, int type, int *irq);
void isa_intr_init(void);
/*
* Miscellanous functions.
*/
void sysbeep(int, int); /* beep with the system speaker */
void isa_fillw(u_int val, void *addr, size_t len);
#endif /* _ARM_ISA_MACHDEP_H_ */

39
sys/arch/arm/include/isapnp_machdep.h
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@ -1,39 +0,0 @@
/* $NetBSD: isapnp_machdep.h,v 1.2 2008/04/28 20:23:14 martin Exp $ */
/*-
* Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center and by Christos Zoulas.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Functions provided to machine-independent ISA PnP code.
*/
int isapnp_map(struct isapnp_softc *);
void isapnp_unmap(struct isapnp_softc *);
int isapnp_map_readport(struct isapnp_softc *);
void isapnp_unmap_readport(struct isapnp_softc *);

3
sys/arch/arm/include/joystick.h
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@ -1,3 +0,0 @@
/* $NetBSD: joystick.h,v 1.1 2013/05/02 03:56:40 matt Exp $ */
#include <sys/joystick.h>

57
sys/arch/arm/include/kcore.h
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@ -1,57 +0,0 @@
/* $NetBSD: kcore.h,v 1.1 2008/01/01 14:06:43 chris Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*
* Modified for NetBSD/i386 by Jason R. Thorpe, Numerical Aerospace
* Simulation Facility, NASA Ames Research Center.
*/
#ifndef _ARM_KCORE_H_
#define _ARM_KCORE_H_
typedef struct cpu_kcore_hdr {
uint32_t version; /* structure version */
uint32_t flags; /* flags */
#define KCORE_ARM_APX 0x0001 /* L1 tables are in APX
format */
uint32_t PAKernelL1Table; /* PA of kernel L1 table */
uint32_t PAUserL1Table; /* PA of userland L1 table */
uint16_t UserL1TableSize; /* size of User L1 table */
uint32_t nmemsegs; /* Number of RAM segments */
uint32_t omemsegs; /* offset to memsegs */
/*
* future versions will add fields here.
*/
#if 0
phys_ram_seg_t memsegs[]; /* RAM segments */
#endif
} cpu_kcore_hdr_t;
#endif /* _ARM_KCORE_H_ */

109
sys/arch/arm/include/limits.h
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@ -1,109 +0,0 @@
/* $NetBSD: limits.h,v 1.18 2014/02/24 16:57:57 christos Exp $ */
/*
* Copyright (c) 1988 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)limits.h 7.2 (Berkeley) 6/28/90
*/
#ifndef _ARM_LIMITS_H_
#define _ARM_LIMITS_H_
#include <sys/featuretest.h>
#define CHAR_BIT 8 /* number of bits in a char */
#define UCHAR_MAX 0xff /* max value for an unsigned char */
#define SCHAR_MAX 0x7f /* max value for a signed char */
#define SCHAR_MIN (-0x7f-1) /* min value for a signed char */
#define USHRT_MAX 0xffff /* max value for an unsigned short */
#define SHRT_MAX 0x7fff /* max value for a short */
#define SHRT_MIN (-0x7fff-1) /* min value for a short */
#define UINT_MAX 0xffffffffU /* max value for an unsigned int */
#define INT_MAX 0x7fffffff /* max value for an int */
#define INT_MIN (-0x7fffffff-1) /* min value for an int */
#ifdef _LP64
#define ULONG_MAX 0xffffffffffffffffUL /* max unsigned long */
#define LONG_MAX 0x7fffffffffffffffL /* max signed long */
#define LONG_MIN (-0x7fffffffffffffffL-1) /* min signed long */
#else
#define ULONG_MAX 0xffffffffUL /* max value for an unsigned long */
#define LONG_MAX 0x7fffffffL /* max value for a long */
#define LONG_MIN (-0x7fffffffL-1) /* min value for a long */
#endif
#if defined(_POSIX_C_SOURCE) || defined(_XOPEN_SOURCE) || \
defined(_NETBSD_SOURCE)
#define SSIZE_MAX LONG_MAX /* max value for a ssize_t */
#if defined(_ISOC99_SOURCE) || (__STDC_VERSION__ - 0) >= 199901L || \
defined(_NETBSD_SOURCE)
#define ULLONG_MAX 0xffffffffffffffffULL /* max unsigned long long */
#define LLONG_MAX 0x7fffffffffffffffLL /* max signed long long */
#define LLONG_MIN (-0x7fffffffffffffffLL-1) /* min signed long long */
#endif
#if defined(_NETBSD_SOURCE)
#define SSIZE_MIN LONG_MIN /* min value for a ssize_t */
#define SIZE_T_MAX ULONG_MAX /* max value for a size_t */
#define UQUAD_MAX 0xffffffffffffffffULL /* max unsigned quad */
#define QUAD_MAX 0x7fffffffffffffffLL /* max signed quad */
#define QUAD_MIN (-0x7fffffffffffffffLL-1) /* min signed quad */
#endif /* _NETBSD_SOURCE */
#endif /* _POSIX_C_SOURCE || _XOPEN_SOURCE || _NETBSD_SOURCE */
#if defined(_XOPEN_SOURCE) || defined(_NETBSD_SOURCE)
#ifdef _LP64
#define LONG_BIT 64
#else
#define LONG_BIT 32
#endif
#define WORD_BIT 32
#define DBL_DIG __DBL_DIG__
#define DBL_MAX __DBL_MAX__
#define DBL_MIN __DBL_MIN__
#define FLT_DIG __FLT_DIG__
#define FLT_MAX __FLT_MAX__
#define FLT_MIN __FLT_MIN__
#ifdef __ARM_PCS_AAPCS64
#define LDBL_DIG __LDBL_DIG__
#define LDBL_MAX __LDBL_MAX__
#define LDBL_MIN __LDBL_MIN__
#endif
#endif /* _XOPEN_SOURCE || _NETBSD_SOURCE */
#endif /* _ARM_LIMITS_H_ */

230
sys/arch/arm/include/lock.h
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@ -1,230 +0,0 @@
/* $NetBSD: lock.h,v 1.32 2015/02/25 13:52:42 joerg Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Machine-dependent spin lock operations.
*
* NOTE: The SWP insn used here is available only on ARM architecture
* version 3 and later (as well as 2a). What we are going to do is
* expect that the kernel will trap and emulate the insn. That will
* be slow, but give us the atomicity that we need.
*/
#ifndef _ARM_LOCK_H_
#define _ARM_LOCK_H_
static __inline int
__SIMPLELOCK_LOCKED_P(__cpu_simple_lock_t *__ptr)
{
return *__ptr == __SIMPLELOCK_LOCKED;
}
static __inline int
__SIMPLELOCK_UNLOCKED_P(__cpu_simple_lock_t *__ptr)
{
return *__ptr == __SIMPLELOCK_UNLOCKED;
}
static __inline void
__cpu_simple_lock_clear(__cpu_simple_lock_t *__ptr)
{
*__ptr = __SIMPLELOCK_UNLOCKED;
}
static __inline void
__cpu_simple_lock_set(__cpu_simple_lock_t *__ptr)
{
*__ptr = __SIMPLELOCK_LOCKED;
}
#ifdef _KERNEL
#include <arm/cpufunc.h>
#define mb_read drain_writebuf /* in cpufunc.h */
#define mb_write drain_writebuf /* in cpufunc.h */
#define mb_memory drain_writebuf /* in cpufunc.h */
#endif
#ifdef _ARM_ARCH_6
static __inline unsigned int
__arm_load_exclusive(__cpu_simple_lock_t *__alp)
{
unsigned int __rv;
if (/*CONSTCOND*/sizeof(*__alp) == 1) {
__asm __volatile("ldrexb\t%0,[%1]" : "=r"(__rv) : "r"(__alp));
} else {
__asm __volatile("ldrex\t%0,[%1]" : "=r"(__rv) : "r"(__alp));
}
return __rv;
}
/* returns 0 on success and 1 on failure */
static __inline unsigned int
__arm_store_exclusive(__cpu_simple_lock_t *__alp, unsigned int __val)
{
unsigned int __rv;
if (/*CONSTCOND*/sizeof(*__alp) == 1) {
__asm __volatile("strexb\t%0,%1,[%2]"
: "=&r"(__rv) : "r"(__val), "r"(__alp) : "cc", "memory");
} else {
__asm __volatile("strex\t%0,%1,[%2]"
: "=&r"(__rv) : "r"(__val), "r"(__alp) : "cc", "memory");
}
return __rv;
}
#elif defined(_KERNEL)
static __inline unsigned char
__swp(unsigned char __val, __cpu_simple_lock_t *__ptr)
{
uint32_t __val32;
__asm volatile("swpb %0, %1, [%2]"
: "=&r" (__val32) : "r" (__val), "r" (__ptr) : "memory");
return __val32;
}
#else
/*
* On MP Cortex, SWP no longer guarantees atomic results. Thus we pad
* out SWP so that when the cpu generates an undefined exception we can replace
* the SWP/MOV instructions with the right LDREX/STREX instructions.
*
* This is why we force the SWP into the template needed for LDREX/STREX
* including the extra instructions and extra register for testing the result.
*/
static __inline int
__swp(int __val, __cpu_simple_lock_t *__ptr)
{
int __tmp, __rv;
__asm volatile(
#if 1
"1:\t" "swp %[__rv], %[__val], [%[__ptr]]"
"\n\t" "b 2f"
#else
"1:\t" "ldrex %[__rv],[%[__ptr]]"
"\n\t" "strex %[__tmp],%[__val],[%[__ptr]]"
#endif
"\n\t" "cmp %[__tmp],#0"
"\n\t" "bne 1b"
"\n" "2:"
: [__rv] "=&r" (__rv), [__tmp] "=&r" (__tmp)
: [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory");
return __rv;
}
#endif /* !_ARM_ARCH_6 */
static __inline void
__arm_membar_producer(void)
{
#ifdef _ARM_ARCH_7
__asm __volatile("dsb" ::: "memory");
#elif defined(_ARM_ARCH_6)
__asm __volatile("mcr\tp15,0,%0,c7,c10,4" :: "r"(0) : "memory");
#endif
}
static __inline void
__arm_membar_consumer(void)
{
#ifdef _ARM_ARCH_7
__asm __volatile("dmb" ::: "memory");
#elif defined(_ARM_ARCH_6)
__asm __volatile("mcr\tp15,0,%0,c7,c10,5" :: "r"(0) : "memory");
#endif
}
static __inline void __unused
__cpu_simple_lock_init(__cpu_simple_lock_t *__alp)
{
*__alp = __SIMPLELOCK_UNLOCKED;
__arm_membar_producer();
}
#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
static __inline void __unused
__cpu_simple_lock(__cpu_simple_lock_t *__alp)
{
#ifdef _ARM_ARCH_6
__arm_membar_consumer();
do {
/* spin */
} while (__arm_load_exclusive(__alp) != __SIMPLELOCK_UNLOCKED
|| __arm_store_exclusive(__alp, __SIMPLELOCK_LOCKED));
__arm_membar_producer();
#else
while (__swp(__SIMPLELOCK_LOCKED, __alp) != __SIMPLELOCK_UNLOCKED)
continue;
#endif
}
#else
void __cpu_simple_lock(__cpu_simple_lock_t *);
#endif
#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
static __inline int __unused
__cpu_simple_lock_try(__cpu_simple_lock_t *__alp)
{
#ifdef _ARM_ARCH_6
__arm_membar_consumer();
do {
if (__arm_load_exclusive(__alp) != __SIMPLELOCK_UNLOCKED) {
return 0;
}
} while (__arm_store_exclusive(__alp, __SIMPLELOCK_LOCKED));
__arm_membar_producer();
return 1;
#else
return (__swp(__SIMPLELOCK_LOCKED, __alp) == __SIMPLELOCK_UNLOCKED);
#endif
}
#else
int __cpu_simple_lock_try(__cpu_simple_lock_t *);
#endif
static __inline void __unused
__cpu_simple_unlock(__cpu_simple_lock_t *__alp)
{
#ifdef _ARM_ARCH_8
if (sizeof(*__alp) == 1) {
__asm __volatile("stlb\t%0, [%1]"
:: "r"(__SIMPLELOCK_UNLOCKED), "r"(__alp) : "memory");
} else {
__asm __volatile("stl\t%0, [%1]"
:: "r"(__SIMPLELOCK_UNLOCKED), "r"(__alp) : "memory");
}
#else
__arm_membar_consumer();
*__alp = __SIMPLELOCK_UNLOCKED;
__arm_membar_producer();
#endif
}
#endif /* _ARM_LOCK_H_ */

322
sys/arch/arm/include/locore.h
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@ -1,322 +0,0 @@
/* $NetBSD: locore.h,v 1.26 2015/06/09 08:13:17 skrll Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* cpu.h
*
* CPU specific symbols
*
* Created : 18/09/94
*
* Based on kate/katelib/arm6.h
*/
#ifndef _ARM_LOCORE_H_
#define _ARM_LOCORE_H_
#ifdef _KERNEL_OPT
#include "opt_cpuoptions.h"
#include "opt_cputypes.h"
#include "opt_arm_debug.h"
#endif
#include <sys/pcu.h>
#include <arm/cpuconf.h>
#include <arm/armreg.h>
#include <machine/frame.h>
#ifdef _LOCORE
#if defined(_ARM_ARCH_6)
#define IRQdisable cpsid i
#define IRQenable cpsie i
#elif defined(__PROG32)
#define IRQdisable \
stmfd sp!, {r0} ; \
mrs r0, cpsr ; \
orr r0, r0, #(I32_bit) ; \
msr cpsr_c, r0 ; \
ldmfd sp!, {r0}
#define IRQenable \
stmfd sp!, {r0} ; \
mrs r0, cpsr ; \
bic r0, r0, #(I32_bit) ; \
msr cpsr_c, r0 ; \
ldmfd sp!, {r0}
#else
/* Not yet used in 26-bit code */
#endif
#if defined (TPIDRPRW_IS_CURCPU)
#define GET_CURCPU(rX) mrc p15, 0, rX, c13, c0, 4
#define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP]
#elif defined (TPIDRPRW_IS_CURLWP)
#define GET_CURLWP(rX) mrc p15, 0, rX, c13, c0, 4
#if defined (MULTIPROCESSOR)
#define GET_CURCPU(rX) GET_CURLWP(rX); ldr rX, [rX, #L_CPU]
#elif defined(_ARM_ARCH_7)
#define GET_CURCPU(rX) movw rX, #:lower16:cpu_info_store; movt rX, #:upper16:cpu_info_store
#else
#define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store)
#endif
#elif !defined(MULTIPROCESSOR)
#define GET_CURCPU(rX) ldr rX, =_C_LABEL(cpu_info_store)
#define GET_CURLWP(rX) GET_CURCPU(rX); ldr rX, [rX, #CI_CURLWP]
#endif
#define GET_CURPCB(rX) GET_CURLWP(rX); ldr rX, [rX, #L_PCB]
#else /* !_LOCORE */
#include <arm/cpufunc.h>
#ifdef __PROG32
#define IRQdisable __set_cpsr_c(I32_bit, I32_bit);
#define IRQenable __set_cpsr_c(I32_bit, 0);
#else
#define IRQdisable set_r15(R15_IRQ_DISABLE, R15_IRQ_DISABLE);
#define IRQenable set_r15(R15_IRQ_DISABLE, 0);
#endif
/*
* Validate a PC or PSR for a user process. Used by various system calls
* that take a context passed by the user and restore it.
*/
#ifdef __PROG32
#ifdef __NO_FIQ
#define VALID_R15_PSR(r15,psr) \
(((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & I32_bit) == 0)
#else
#define VALID_R15_PSR(r15,psr) \
(((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & IF32_bits) == 0)
#endif
#else
#define VALID_R15_PSR(r15,psr) \
(((r15) & R15_MODE) == R15_MODE_USR && \
((r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)) == 0)
#endif
/*
* Translation Table Base Register Share/Cache settings
*/
#define TTBR_UPATTR (TTBR_S | TTBR_RGN_WBNWA | TTBR_C)
#define TTBR_MPATTR (TTBR_S | TTBR_RGN_WBNWA /* | TTBR_NOS */ | TTBR_IRGN_WBNWA)
/* The address of the vector page. */
extern vaddr_t vector_page;
#ifdef __PROG32
void arm32_vector_init(vaddr_t, int);
#define ARM_VEC_RESET (1 << 0)
#define ARM_VEC_UNDEFINED (1 << 1)
#define ARM_VEC_SWI (1 << 2)
#define ARM_VEC_PREFETCH_ABORT (1 << 3)
#define ARM_VEC_DATA_ABORT (1 << 4)
#define ARM_VEC_ADDRESS_EXCEPTION (1 << 5)
#define ARM_VEC_IRQ (1 << 6)
#define ARM_VEC_FIQ (1 << 7)
#define ARM_NVEC 8
#define ARM_VEC_ALL 0xffffffff
#endif /* __PROG32 */
#ifndef acorn26
/*
* cpu device glue (belongs in cpuvar.h)
*/
void cpu_attach(device_t, cpuid_t);
#endif
/* 1 == use cpu_sleep(), 0 == don't */
extern int cpu_do_powersave;
extern int cpu_printfataltraps;
extern int cpu_fpu_present;
extern int cpu_hwdiv_present;
extern int cpu_neon_present;
extern int cpu_simd_present;
extern int cpu_simdex_present;
extern int cpu_umull_present;
extern int cpu_synchprim_present;
extern int cpu_instruction_set_attributes[6];
extern int cpu_memory_model_features[4];
extern int cpu_processor_features[2];
extern int cpu_media_and_vfp_features[2];
extern bool arm_has_tlbiasid_p;
#ifdef MULTIPROCESSOR
extern u_int arm_cpu_max;
extern volatile u_int arm_cpu_hatched;
#endif
#if !defined(CPU_ARMV7)
#define CPU_IS_ARMV7_P() false
#elif defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6)
extern bool cpu_armv7_p;
#define CPU_IS_ARMV7_P() (cpu_armv7_p)
#else
#define CPU_IS_ARMV7_P() true
#endif
#if !defined(CPU_ARMV6)
#define CPU_IS_ARMV6_P() false
#elif defined(CPU_ARMV7) || defined(CPU_PRE_ARMV6)
extern bool cpu_armv6_p;
#define CPU_IS_ARMV6_P() (cpu_armv6_p)
#else
#define CPU_IS_ARMV6_P() true
#endif
/*
* Used by the fault code to read the current instruction.
*/
static inline uint32_t
read_insn(vaddr_t va, bool user_p)
{
uint32_t insn;
if (user_p) {
__asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va));
} else {
insn = *(const uint32_t *)va;
}
#if defined(__ARMEB__) && defined(_ARM_ARCH_7)
insn = bswap32(insn);
#endif
return insn;
}
/*
* Used by the fault code to read the current thumb instruction.
*/
static inline uint32_t
read_thumb_insn(vaddr_t va, bool user_p)
{
va &= ~1;
uint32_t insn;
if (user_p) {
#if defined(__thumb__) && defined(_ARM_ARCH_T2)
__asm __volatile("ldrht %0, [%1, #0]" : "=&r"(insn) : "r"(va));
#elif defined(_ARM_ARCH_7)
__asm __volatile("ldrht %0, [%1], #0" : "=&r"(insn) : "r"(va));
#else
__asm __volatile("ldrt %0, [%1]" : "=&r"(insn) : "r"(va & ~3));
#ifdef __ARMEB__
insn = (uint16_t) (insn >> (((va ^ 2) & 2) << 3));
#else
insn = (uint16_t) (insn >> ((va & 2) << 3));
#endif
#endif
} else {
insn = *(const uint16_t *)va;
}
#if defined(__ARMEB__) && defined(_ARM_ARCH_7)
insn = bswap16(insn);
#endif
return insn;
}
#ifndef _RUMPKERNEL
static inline void
arm_dmb(void)
{
if (CPU_IS_ARMV6_P())
armreg_dmb_write(0);
else if (CPU_IS_ARMV7_P())
__asm __volatile("dmb" ::: "memory");
}
static inline void
arm_dsb(void)
{
if (CPU_IS_ARMV6_P())
armreg_dsb_write(0);
else if (CPU_IS_ARMV7_P())
__asm __volatile("dsb" ::: "memory");
}
static inline void
arm_isb(void)
{
if (CPU_IS_ARMV6_P())
armreg_isb_write(0);
else if (CPU_IS_ARMV7_P())
__asm __volatile("isb" ::: "memory");
}
#endif
/*
* Random cruft
*/
struct lwp;
/* cpu.c */
void identify_arm_cpu(device_t, struct cpu_info *);
/* cpuswitch.S */
struct pcb;
void savectx(struct pcb *);
/* ast.c */
void userret(struct lwp *);
/* *_machdep.c */
void bootsync(void);
/* fault.c */
int badaddr_read(void *, size_t, void *);
/* syscall.c */
void swi_handler(trapframe_t *);
/* arm_machdep.c */
void ucas_ras_check(trapframe_t *);
/* vfp_init.c */
void vfp_attach(struct cpu_info *);
void vfp_discardcontext(bool);
void vfp_savecontext(void);
void vfp_kernel_acquire(void);
void vfp_kernel_release(void);
bool vfp_used_p(void);
extern const pcu_ops_t arm_vfp_ops;
#endif /* !_LOCORE */
#endif /* !_ARM_LOCORE_H_ */

6
sys/arch/arm/include/math.h
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@ -1,6 +0,0 @@
/* $NetBSD: math.h,v 1.4 2014/01/31 19:38:06 matt Exp $ */
#define __HAVE_NANF
#ifdef __ARM_PCS_AAPCS64
#define __HAVE_LONG_DOUBLE 128
#endif

190
sys/arch/arm/include/mcontext.h
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@ -1,190 +0,0 @@
/* $NetBSD: mcontext.h,v 1.18 2015/03/24 08:38:29 matt Exp $ */
/*-
* Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein and by Jason R. Thorpe of Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_MCONTEXT_H_
#define _ARM_MCONTEXT_H_
#include <sys/stdint.h>
/*
* General register state
*/
#define _NGREG 17
typedef unsigned int __greg_t;
typedef __greg_t __gregset_t[_NGREG];
#define _REG_R0 0
#define _REG_R1 1
#define _REG_R2 2
#define _REG_R3 3
#define _REG_R4 4
#define _REG_R5 5
#define _REG_R6 6
#define _REG_R7 7
#define _REG_R8 8
#define _REG_R9 9
#define _REG_R10 10
#define _REG_R11 11
#define _REG_R12 12
#define _REG_R13 13
#define _REG_R14 14
#define _REG_R15 15
#define _REG_CPSR 16
/* Convenience synonyms */
#define _REG_FP _REG_R11
#define _REG_SP _REG_R13
#define _REG_LR _REG_R14
#define _REG_PC _REG_R15
/*
* Floating point register state
*/
/* Note: the storage layout of this structure must be identical to ARMFPE! */
typedef struct {
unsigned int __fp_fpsr;
struct {
unsigned int __fp_exponent;
unsigned int __fp_mantissa_hi;
unsigned int __fp_mantissa_lo;
} __fp_fr[8];
} __fpregset_t;
typedef struct {
#ifdef __ARM_EABI__
unsigned int __vfp_fpscr;
uint64_t __vfp_fstmx[32];
unsigned int __vfp_fpsid;
#else
unsigned int __vfp_fpscr;
unsigned int __vfp_fstmx[33];
unsigned int __vfp_fpsid;
#endif
} __vfpregset_t;
typedef struct {
__gregset_t __gregs;
union {
__fpregset_t __fpregs;
__vfpregset_t __vfpregs;
} __fpu;
#if defined(__minix)
int mc_flags;
int mc_magic;
#else
__greg_t _mc_tlsbase;
__greg_t _mc_user_tpid;
#endif /* defined(__minix) */
} mcontext_t, mcontext32_t;
/* Machine-dependent uc_flags */
#define _UC_ARM_VFP 0x00010000 /* FPU field is VFP */
/* used by signal delivery to indicate status of signal stack */
#define _UC_SETSTACK 0x00020000
#define _UC_CLRSTACK 0x00040000
#define _UC_TLSBASE 0x00080000
#define _UC_MACHINE_PAD 1 /* Padding appended to ucontext_t */
#define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_SP])
#define _UC_MACHINE_PC(uc) ((uc)->uc_mcontext.__gregs[_REG_PC])
#define _UC_MACHINE_INTRV(uc) ((uc)->uc_mcontext.__gregs[_REG_R0])
#define _UC_MACHINE_SET_PC(uc, pc) _UC_MACHINE_PC(uc) = (pc)
#if defined(__minix)
#define _UC_MACHINE_STACK(uc) ((uc)->uc_mcontext.__gregs[_REG_SP])
#define _UC_MACHINE_SET_STACK(uc, sp) _UC_MACHINE_STACK(uc) = (sp)
#define _UC_MACHINE_FP(uc) ((uc)->uc_mcontext.__gregs[_REG_FP])
#define _UC_MACHINE_SET_FP(uc, fp) _UC_MACHINE_FP(uc) = (fp)
#define _UC_MACHINE_LR(uc) ((uc)->uc_mcontext.__gregs[_REG_LR])
#define _UC_MACHINE_SET_LR(uc, lr) _UC_MACHINE_LR(uc) = (lr)
#define _UC_MACHINE_R0(uc) ((uc)->uc_mcontext.__gregs[_REG_R0])
#define _UC_MACHINE_SET_R0(uc, setreg) _UC_MACHINE_R0(uc) = (setreg)
#define _UC_MACHINE_R1(uc) ((uc)->uc_mcontext.__gregs[_REG_R1])
#define _UC_MACHINE_SET_R1(uc, setreg) _UC_MACHINE_R1(uc) = (setreg)
#define _UC_MACHINE_R2(uc) ((uc)->uc_mcontext.__gregs[_REG_R2])
#define _UC_MACHINE_SET_R2(uc, setreg) _UC_MACHINE_R2(uc) = (setreg)
#define _UC_MACHINE_R3(uc) ((uc)->uc_mcontext.__gregs[_REG_R3])
#define _UC_MACHINE_SET_R3(uc, setreg) _UC_MACHINE_R3(uc) = (setreg)
#define _UC_MACHINE_R4(uc) ((uc)->uc_mcontext.__gregs[_REG_R4])
#define _UC_MACHINE_SET_R4(uc, setreg) _UC_MACHINE_R4(uc) = (setreg)
#endif /* defined(__minix) */
#ifdef __ARM_EABI__
#define __UCONTEXT_SIZE (256 + 144)
#else
#define __UCONTEXT_SIZE 256
#endif
__BEGIN_DECLS
static __inline void *
__lwp_getprivate_fast(void)
{
#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
extern void *_lwp_getprivate(void);
void *rv;
__asm("mrc p15, 0, %0, c13, c0, 3" : "=r"(rv));
if (__predict_true(rv))
return rv;
/*
* Some ARM cores are broken and don't raise an undefined fault when an
* unrecogized mrc instruction is encountered, but just return zero.
* To do deal with that, if we get a zero we (re-)fetch the value using
* syscall.
*/
return _lwp_getprivate();
#else
extern void *__aeabi_read_tp(void);
return __aeabi_read_tp();
#endif /* !__thumb__ || _ARM_ARCH_T2 */
}
#if defined(_KERNEL)
void vfp_getcontext(struct lwp *, mcontext_t *, int *);
void vfp_setcontext(struct lwp *, const mcontext_t *);
#endif
#if defined(__minix)
int setmcontext(const mcontext_t *mcp);
int getmcontext(mcontext_t *mcp);
#define MCF_MAGIC 0xc0ffee
#endif /* defined(__minix) */
__END_DECLS
#endif /* !_ARM_MCONTEXT_H_ */

120
sys/arch/arm/include/mutex.h
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@ -1,120 +0,0 @@
/* $NetBSD: mutex.h,v 1.20 2015/02/25 13:52:42 joerg Exp $ */
/*-
* Copyright (c) 2002, 2007 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe and Andrew Doran.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_MUTEX_H_
#define _ARM_MUTEX_H_
/*
* The ARM mutex implementation is troublesome, because pre-v6 ARM lacks a
* compare-and-swap operation. However, there aren't any MP pre-v6 ARM
* systems to speak of.
*
* ARMv6 and later, however, does have ldrex/strex, and can thus implement an
* MP-safe compare-and-swap.
*
* So, what we have done is implement simple mutexes using a compare-and-swap.
* We support pre-ARMv6 by implementing CAS as a restartable atomic sequence
* that is checked by the IRQ vector.
*
*/
#ifndef __MUTEX_PRIVATE
struct kmutex {
uintptr_t mtx_pad1;
};
#else /* __MUTEX_PRIVATE */
struct kmutex {
union {
/* Adaptive mutex */
volatile uintptr_t mtxa_owner; /* 0-3 */
/* Spin mutex */
struct {
/*
* Since the low bit of mtxa_owner is used to flag this
* mutex as a spin mutex, we can't use the first byte
* or the last byte to store the ipl or lock values.
*/
volatile uint8_t mtxs_dummy;
ipl_cookie_t mtxs_ipl;
__cpu_simple_lock_t mtxs_lock;
volatile uint8_t mtxs_unused;
} s;
} u;
};
#define mtx_owner u.mtxa_owner
#define mtx_ipl u.s.mtxs_ipl
#define mtx_lock u.s.mtxs_lock
#if 0
#define __HAVE_MUTEX_STUBS 1
#define __HAVE_SPIN_MUTEX_STUBS 1
#endif
#define __HAVE_SIMPLE_MUTEXES 1
/*
* MUTEX_{GIVE,RECEIVE}: no memory barrier is required in the UP case;
* we're synchronizing against interrupts, not multiple processors.
*/
#ifdef MULTIPROCESSOR
#ifdef _ARM_ARCH_7
#define MUTEX_RECEIVE(mtx) __asm __volatile("dmb" ::: "memory")
#else
#define MUTEX_RECEIVE(mtx) membar_consumer()
#endif
#else
#define MUTEX_RECEIVE(mtx) /* nothing */
#endif
#ifdef MULTIPROCESSOR
#ifdef _ARM_ARCH_7
#define MUTEX_GIVE(mtx) __asm __volatile("dsb" ::: "memory")
#else
#define MUTEX_GIVE(mtx) membar_producer()
#endif
#else
#define MUTEX_GIVE(mtx) /* nothing */
#endif
#define MUTEX_CAS(p, o, n) \
(atomic_cas_ulong((volatile unsigned long *)(p), (o), (n)) == (o))
#ifdef MULTIPROCESSOR
#define MUTEX_SMT_PAUSE() __asm __volatile("wfe")
#define MUTEX_SMT_WAKE() __asm __volatile("sev")
#endif
#endif /* __MUTEX_PRIVATE */
#endif /* _ARM_MUTEX_H_ */

85
sys/arch/arm/include/ofisa_machdep.h
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@ -1,85 +0,0 @@
/* $NetBSD: ofisa_machdep.h,v 1.3 2012/10/27 17:17:39 chs Exp $ */
/*
* Copyright 1998
* Digital Equipment Corporation. All rights reserved.
*
* This software is furnished under license and may be used and
* copied only in accordance with the following terms and conditions.
* Subject to these conditions, you may download, copy, install,
* use, modify and distribute this software in source and/or binary
* form. No title or ownership is transferred hereby.
*
* 1) Any source code used, modified or distributed must reproduce
* and retain this copyright notice and list of conditions as
* they appear in the source file.
*
* 2) No right is granted to use any trade name, trademark, or logo of
* Digital Equipment Corporation. Neither the "Digital Equipment
* Corporation" name nor any trademark or logo of Digital Equipment
* Corporation may be used to endorse or promote products derived
* from this software without the prior written permission of
* Digital Equipment Corporation.
*
* 3) This software is provided "AS-IS" and any express or implied
* warranties, including but not limited to, any implied warranties
* of merchantability, fitness for a particular purpose, or
* non-infringement are disclaimed. In no event shall DIGITAL be
* liable for any damages whatsoever, and in particular, DIGITAL
* shall not be liable for special, indirect, consequential, or
* incidental damages or damages for lost profits, loss of
* revenue or loss of use, whether such damages arise in contract,
* negligence, tort, under statute, in equity, at law or otherwise,
* even if advised of the possibility of such damage.
*/
int ofisa_get_isabus_data(int, struct isabus_attach_args *);
int ofisa_ignore_child(int pphandle, int cphandle);
#if defined(_KERNEL_OPT)
#include "opt_compat_old_ofw.h"
#endif
#ifdef COMPAT_OLD_OFW
#define _OFISA_MD_MATCH
int ofisa_md_match(device_t, cfdata_t, void *);
#define _COM_OFISA_MD_MATCH
#define _COM_OFISA_MD_INTR_FIXUP
int com_ofisa_md_match(device_t, cfdata_t, void *);
int com_ofisa_md_intr_fixup(device_t, device_t, void *,
struct ofisa_intr_desc *, int, int);
#define _CS_OFISA_MD_MATCH
#define _CS_OFISA_MD_REG_FIXUP
#define _CS_OFISA_MD_INTR_FIXUP
#define _CS_OFISA_MD_DMA_FIXUP
#define _CS_OFISA_MD_MEDIA_FIXUP
int cs_ofisa_md_match(device_t, cfdata_t, void *);
int cs_ofisa_md_reg_fixup(device_t, device_t, void *,
struct ofisa_reg_desc *, int, int);
int cs_ofisa_md_intr_fixup(device_t, device_t, void *,
struct ofisa_intr_desc *, int, int);
int cs_ofisa_md_dma_fixup(device_t, device_t, void *,
struct ofisa_dma_desc *, int, int);
int *cs_ofisa_md_media_fixup(device_t, device_t, void *,
int *, int *, int *);
#define _LPT_OFISA_MD_MATCH
#define _LPT_OFISA_MD_INTR_FIXUP
int lpt_ofisa_md_match(device_t, cfdata_t, void *);
int lpt_ofisa_md_intr_fixup(device_t, device_t, void *,
struct ofisa_intr_desc *, int, int);
#define _WDC_OFISA_MD_MATCH
#define _WDC_OFISA_MD_INTR_FIXUP
int wdc_ofisa_md_match(device_t, cfdata_t, void *);
int wdc_ofisa_md_intr_fixup(device_t, device_t, void *,
struct ofisa_intr_desc *, int, int);
#endif /* COMPAT_OLD_OFW */
/* The following aren't dependent on old OpenFirmware. */
#define _CS_OFISA_MD_CFGFLAGS_FIXUP
int cs_ofisa_md_cfgflags_fixup(device_t, device_t, void *);

69
sys/arch/arm/include/ofw.h
View File

@ -1,69 +0,0 @@
/* $NetBSD: ofw.h,v 1.5 2014/09/13 17:41:03 matt Exp $ */
/*
* Copyright 1997
* Digital Equipment Corporation. All rights reserved.
*
* This software is furnished under license and may be used and
* copied only in accordance with the following terms and conditions.
* Subject to these conditions, you may download, copy, install,
* use, modify and distribute this software in source and/or binary
* form. No title or ownership is transferred hereby.
*
* 1) Any source code used, modified or distributed must reproduce
* and retain this copyright notice and list of conditions as
* they appear in the source file.
*
* 2) No right is granted to use any trade name, trademark, or logo of
* Digital Equipment Corporation. Neither the "Digital Equipment
* Corporation" name nor any trademark or logo of Digital Equipment
* Corporation may be used to endorse or promote products derived
* from this software without the prior written permission of
* Digital Equipment Corporation.
*
* 3) This software is provided "AS-IS" and any express or implied
* warranties, including but not limited to, any implied warranties
* of merchantability, fitness for a particular purpose, or
* non-infringement are disclaimed. In no event shall DIGITAL be
* liable for any damages whatsoever, and in particular, DIGITAL
* shall not be liable for special, indirect, consequential, or
* incidental damages or damages for lost profits, loss of
* revenue or loss of use, whether such damages arise in contract,
* negligence, tort, under statute, in equity, at law or otherwise,
* even if advised of the possibility of such damage.
*/
#ifndef _ARM_OFW_H_
#define _ARM_OFW_H_
/* Virtual address range reserved for OFW. */
/* Maybe this should be elsewhere? -JJK */
#define OFW_VIRT_BASE 0xF7000000
#define OFW_VIRT_SIZE 0x01000000
/* OFW client services handle. */
typedef int (*ofw_handle_t)(void *);
/* Implemented in <ofw/ofw.c> */
void ofw_init(ofw_handle_t);
void ofw_boot(int, char *);
void ofw_getbootinfo(char **, char **);
void ofw_configmem(void);
void ofw_configisa(vaddr_t *, vaddr_t *);
void ofw_configisadma(vaddr_t *);
int ofw_isadmarangeintersect(vaddr_t, vaddr_t, vaddr_t *, vaddr_t *);
vaddr_t ofw_gettranslation(vaddr_t);
vaddr_t ofw_map(vaddr_t, vsize_t, int);
vaddr_t ofw_getcleaninfo(void);
#ifdef OFWGENCFG
/* Implemented in <ofw/ofwgencfg_machdep.c> */
extern int ofw_handleticks;
extern void cpu_reboot(int, char *);
extern void ofrootfound(void);
#endif
#endif /* !_ARM_OFW_H_ */

199
sys/arch/arm/include/param.h
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@ -1,199 +0,0 @@
/* $NetBSD: param.h,v 1.19 2013/10/26 18:07:52 matt Exp $ */
/*
* Copyright (c) 1994,1995 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the RiscBSD team.
* 4. The name "RiscBSD" nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ARM_PARAM_H_
#define _ARM_PARAM_H_
/*
* Machine dependent constants for all ARM processors
*/
/*
* For KERNEL code:
* MACHINE must be defined by the individual port. This is so that
* uname returns the correct thing, etc.
*
* MACHINE_ARCH may be defined by individual ports as a temporary
* measure while we're finishing the conversion to ELF.
*
* For non-KERNEL code:
* If ELF, MACHINE and MACHINE_ARCH are forced to "arm/armeb".
*/
#if defined(_KERNEL)
# ifndef MACHINE_ARCH /* XXX For now */
# ifndef __ARMEB__
# ifdef __ARM_EABI__
# define _MACHINE_ARCH earm
# define MACHINE_ARCH "earm"
# else
# define _MACHINE_ARCH arm
# define MACHINE_ARCH "arm"
# endif
# else
# ifdef __ARM_EABI__
# define _MACHINE_ARCH earmeb
# define MACHINE_ARCH "earmeb"
# else
# define _MACHINE_ARCH armeb
# define MACHINE_ARCH "armeb"
# endif
# endif /* __ARMEB__ */
# endif /* MACHINE_ARCH */
#else
# undef _MACHINE
# undef MACHINE
# undef _MACHINE_ARCH
# undef MACHINE_ARCH
# define _MACHINE arm
# define MACHINE "arm"
# ifndef __ARMEB__
# ifdef __ARM_EABI__
# ifdef __ARM_PCS_VFP
# ifdef _ARM_ARCH_7
# define _MACHINE_ARCH earmv7hf
# define MACHINE_ARCH "earmv7hf"
# elif defined(_ARM_ARCH_6)
# define _MACHINE_ARCH earmv6hf
# define MACHINE_ARCH "earmv6hf"
# else
# define _MACHINE_ARCH earmhf
# define MACHINE_ARCH "earmhf"
# endif
# else
# ifdef _ARM_ARCH_7
# define _MACHINE_ARCH earmv7
# define MACHINE_ARCH "earmv7"
# elif defined(_ARM_ARCH_6)
# define _MACHINE_ARCH earmv6
# define MACHINE_ARCH "earmv6"
# elif !defined(_ARM_ARCH_5T)
# define _MACHINE_ARCH earmv4
# define MACHINE_ARCH "earmv4"
# else
# define _MACHINE_ARCH earm
# define MACHINE_ARCH "earm"
# endif
# endif
# else
# define _MACHINE_ARCH arm
# define MACHINE_ARCH "arm"
# endif
# else
# ifdef __ARM_EABI__
# ifdef __ARM_PCS_VFP
# ifdef _ARM_ARCH_7
# define _MACHINE_ARCH earmv7hfeb
# define MACHINE_ARCH "earmv7hfeb"
# elif defined(_ARM_ARCH_6)
# define _MACHINE_ARCH earmv6hfeb
# define MACHINE_ARCH "earmv6hfeb"
# else
# define _MACHINE_ARCH earmhfeb
# define MACHINE_ARCH "earmhfeb"
# endif
# else
# ifdef _ARM_ARCH_7
# define _MACHINE_ARCH earmv7eb
# define MACHINE_ARCH "earmv7eb"
# elif defined(_ARM_ARCH_6)
# define _MACHINE_ARCH earmv6eb
# define MACHINE_ARCH "earmv6eb"
# elif !defined(_ARM_ARCH_5T)
# define _MACHINE_ARCH earmv4eb
# define MACHINE_ARCH "earmv4eb"
# else
# define _MACHINE_ARCH earmeb
# define MACHINE_ARCH "earmeb"
# endif
# endif
# else
# define _MACHINE_ARCH armeb
# define MACHINE_ARCH "armeb"
# endif
# endif /* __ARMEB__ */
#endif /* !_KERNEL */
#define MID_MACHINE MID_ARM6
/* ARM-specific macro to align a stack pointer (downwards). */
#define STACK_ALIGNBYTES (8 - 1)
#ifdef __ARM_EABI__
#define ALIGNBYTES32 3
#else
#define ALIGNBYTES32 7
#endif
#define DEV_BSHIFT 9 /* log2(DEV_BSIZE) */
#define DEV_BSIZE (1 << DEV_BSHIFT)
#define BLKDEV_IOSIZE 2048
#ifndef MAXPHYS
#define MAXPHYS 65536 /* max I/O transfer size */
#endif
/*
* Constants related to network buffer management.
* MCLBYTES must be no larger than NBPG (the software page size), and,
* on machines that exchange pages of input or output buffers with mbuf
* clusters (MAPPED_MBUFS), MCLBYTES must also be an integral multiple
* of the hardware page size.
*/
#define MSIZE 256 /* size of an mbuf */
#ifndef MCLSHIFT
#define MCLSHIFT 11 /* convert bytes to m_buf clusters */
/* 2K cluster can hold Ether frame */
#endif /* MCLSHIFT */
#define MCLBYTES (1 << MCLSHIFT) /* size of a m_buf cluster */
#ifndef NMBCLUSTERS_MAX
#define NMBCLUSTERS_MAX (0x2000000 / MCLBYTES) /* Limit to 64MB for clusters */
#endif
/*
* Compatibility /dev/zero mapping.
*/
#ifdef _KERNEL
#ifdef COMPAT_16
#define COMPAT_ZERODEV(x) (x == makedev(0, _DEV_ZERO_oARM))
#endif
#endif /* _KERNEL */
#if defined(__minix)
/* LSC: FIXME This is a hack. Good enough for now, as we only have ARMv7 targets. */
#include <arm/arm32/param.h>
#endif /* defined(__minix) */
#endif /* _ARM_PARAM_H_ */

105
sys/arch/arm/include/pcb.h
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@ -1,105 +0,0 @@
/* pcb.h,v 1.14.22.2 2007/11/06 23:15:05 matt Exp */
/*
* Copyright (c) 2001 Matt Thomas <matt@3am-software.com>.
* Copyright (c) 1994 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the RiscBSD team.
* 4. The name "RiscBSD" nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ARM_PCB_H_
#define _ARM_PCB_H_
#include <machine/frame.h>
#include <arm/arm32/pte.h>
#include <arm/reg.h>
struct pcb_arm32 {
/*
* WARNING!
* cpuswitchto.S relies on pcb32_r8 being quad-aligned in struct pcb
* (due to the use of "strd" when compiled for XSCALE)
*/
u_int pcb32_r8 __aligned(8); /* used */
u_int pcb32_r9; /* used */
u_int pcb32_r10; /* used */
u_int pcb32_r11; /* used */
u_int pcb32_r12; /* used */
u_int pcb32_sp; /* used */
u_int pcb32_lr;
u_int pcb32_pc;
/*
* ARMv6 has two user thread/process id registers which can hold
* any 32bit quanttiies.
*/
u_int pcb32_user_pid_rw; /* p15, 0, Rd, c13, c0, 2 */
u_int pcb32_user_pid_ro; /* p15, 0, Rd, c13, c0, 3 */
};
#define pcb_pagedir pcb_un.un_32.pcb32_pagedir
#define pcb_pl1vec pcb_un.un_32.pcb32_pl1vec
#define pcb_l1vec pcb_un.un_32.pcb32_l1vec
#define pcb_dacr pcb_un.un_32.pcb32_dacr
#define pcb_cstate pcb_un.un_32.pcb32_cstate
#define pcb_user_pid_rw pcb_un.un_32.pcb32_user_pid_rw
#ifdef __PROG32
#define pcb_ksp pcb_un.un_32.pcb32_sp
#endif
struct pcb_arm26 {
struct switchframe *pcb26_sf;
};
#define pcb_sf pcb_un.un_26.pcb26_sf
#ifdef __PROG26
#define pcb_ksp pcb_sf.sf_r13
#endif
/*
* WARNING!
* See warning for struct pcb_arm32, above, before changing struct pcb!
*/
struct pcb {
union {
struct pcb_arm32 un_32;
struct pcb_arm26 un_26;
} pcb_un;
void * pcb_onfault; /* On fault handler */
struct vfpreg pcb_vfp; /* VFP registers */
struct vfpreg pcb_kernel_vfp; /* kernel VFP state */
};
/*
* No additional data for core dumps.
*/
struct md_coredump {
int md_empty;
};
#endif /* _ARM_PCB_H_ */

117
sys/arch/arm/include/pci_machdep.h
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@ -1,117 +0,0 @@
/* $NetBSD: pci_machdep.h,v 1.10 2014/03/29 19:28:26 christos Exp $ */
/*
* Modified for arm32 by Mark Brinicombe
*
* from: sys/arch/alpha/pci/pci_machdep.h
*
* Copyright (c) 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#ifndef _ARM_PCI_MACHDEP_H_
#define _ARM_PCI_MACHDEP_H_
/*
* Machine-specific definitions for PCI autoconfiguration.
*/
/*
* Types provided to machine-independent PCI code
*/
typedef struct arm32_pci_chipset *pci_chipset_tag_t;
typedef u_long pcitag_t;
typedef u_long pci_intr_handle_t;
/*
* Forward declarations.
*/
struct pci_attach_args;
/*
* arm32-specific PCI structure and type definitions.
* NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
*/
struct arm32_pci_chipset {
void *pc_conf_v;
void (*pc_attach_hook)(device_t, device_t,
struct pcibus_attach_args *);
int (*pc_bus_maxdevs)(void *, int);
pcitag_t (*pc_make_tag)(void *, int, int, int);
void (*pc_decompose_tag)(void *, pcitag_t, int *,
int *, int *);
pcireg_t (*pc_conf_read)(void *, pcitag_t, int);
void (*pc_conf_write)(void *, pcitag_t, int, pcireg_t);
void *pc_intr_v;
int (*pc_intr_map)(const struct pci_attach_args *,
pci_intr_handle_t *);
const char *(*pc_intr_string)(void *, pci_intr_handle_t,
char *, size_t);
const struct evcnt *(*pc_intr_evcnt)(void *, pci_intr_handle_t);
void *(*pc_intr_establish)(void *, pci_intr_handle_t,
int, int (*)(void *), void *);
void (*pc_intr_disestablish)(void *, void *);
#ifdef __HAVE_PCI_CONF_HOOK
int (*pc_conf_hook)(void *, int, int, int, pcireg_t);
#endif
void (*pc_conf_interrupt)(void *, int, int, int, int, int *);
uint32_t pc_cfg_cmd;
};
/*
* Functions provided to machine-independent PCI code.
*/
#define pci_attach_hook(p, s, pba) \
(*(pba)->pba_pc->pc_attach_hook)((p), (s), (pba))
#define pci_bus_maxdevs(c, b) \
(*(c)->pc_bus_maxdevs)((c)->pc_conf_v, (b))
#define pci_make_tag(c, b, d, f) \
(*(c)->pc_make_tag)((c)->pc_conf_v, (b), (d), (f))
#define pci_decompose_tag(c, t, bp, dp, fp) \
(*(c)->pc_decompose_tag)((c)->pc_conf_v, (t), (bp), (dp), (fp))
#define pci_conf_read(c, t, r) \
(*(c)->pc_conf_read)((c)->pc_conf_v, (t), (r))
#define pci_conf_write(c, t, r, v) \
(*(c)->pc_conf_write)((c)->pc_conf_v, (t), (r), (v))
#define pci_intr_map(pa, ihp) \
(*(pa)->pa_pc->pc_intr_map)((pa), (ihp))
#define pci_intr_string(c, ih, buf, len) \
(*(c)->pc_intr_string)((c)->pc_intr_v, (ih), (buf), (len))
#define pci_intr_evcnt(c, ih) \
(*(c)->pc_intr_evcnt)((c)->pc_intr_v, (ih))
#define pci_intr_establish(c, ih, l, h, a) \
(*(c)->pc_intr_establish)((c)->pc_intr_v, (ih), (l), (h), (a))
#define pci_intr_disestablish(c, iv) \
(*(c)->pc_intr_disestablish)((c)->pc_intr_v, (iv))
#ifdef __HAVE_PCI_CONF_HOOK
#define pci_conf_hook(c, b, d, f, id) \
(*(c)->pc_conf_hook)((c)->pc_conf_v, (b), (d), (f), (id))
#endif
#define pci_conf_interrupt(c, b, d, i, s, p) \
(*(c)->pc_conf_interrupt)((c)->pc_conf_v, (b), (d), (i), (s), (p))
#endif /* _ARM_PCI_MACHDEP_H_ */

46
sys/arch/arm/include/pio.h
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@ -1,46 +0,0 @@
/* $NetBSD: pio.h,v 1.3 2014/01/29 00:42:15 matt Exp $ */
/*
* Copyright 1997
* Digital Equipment Corporation. All rights reserved.
*
* This software is furnished under license and may be used and
* copied only in accordance with the following terms and conditions.
* Subject to these conditions, you may download, copy, install,
* use, modify and distribute this software in source and/or binary
* form. No title or ownership is transferred hereby.
*
* 1) Any source code used, modified or distributed must reproduce
* and retain this copyright notice and list of conditions as
* they appear in the source file.
*
* 2) No right is granted to use any trade name, trademark, or logo of
* Digital Equipment Corporation. Neither the "Digital Equipment
* Corporation" name nor any trademark or logo of Digital Equipment
* Corporation may be used to endorse or promote products derived
* from this software without the prior written permission of
* Digital Equipment Corporation.
*
* 3) This software is provided "AS-IS" and any express or implied
* warranties, including but not limited to, any implied warranties
* of merchantability, fitness for a particular purpose, or
* non-infringement are disclaimed. In no event shall DIGITAL be
* liable for any damages whatsoever, and in particular, DIGITAL
* shall not be liable for special, indirect, consequential, or
* incidental damages or damages for lost profits, loss of
* revenue or loss of use, whether such damages arise in contract,
* negligence, tort, under statute, in equity, at law or otherwise,
* even if advised of the possibility of such damage.
*/
#ifndef _ARM_PIO_H_
#define _ARM_PIO_H_
#include <sys/bus.h>
extern struct bus_space isa_io_bs_tag;
#define inb(port) bus_space_read_1( &isa_io_bs_tag, (bus_space_handle_t)isa_io_bs_tag.bs_cookie, (port))
#define outb(port, byte) bus_space_write_1(&isa_io_bs_tag, (bus_space_handle_t)isa_io_bs_tag.bs_cookie, (port), (byte))
#endif /* _ARM_PIO_H_ */

94
sys/arch/arm/include/pmc.h
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@ -1,94 +0,0 @@
/* $NetBSD: pmc.h,v 1.3 2002/08/09 05:27:10 thorpej Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Allen Briggs for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_PMC_H_
#define _ARM_PMC_H_
#define PMC_CLASS_I80200 0x10000 /* i80200-compatible */
#define PMC_TYPE_I80200_CCNT 0x10001 /* cycle counter */
#define PMC_TYPE_I80200_PMCx 0x10002 /* performance counter */
#if defined(_KERNEL)
#include <arm/cpuconf.h>
struct arm_pmc_funcs {
void (*fork)(struct proc *p1, struct proc *p2);
int (*num_counters)(void);
int (*counter_type)(int ctr);
void (*save_context)(struct proc *p);
void (*restore_context)(struct proc *p);
void (*enable_counter)(struct proc *p, int ctr);
void (*disable_counter)(struct proc *p, int ctr);
void (*accumulate)(struct proc *parent, struct proc *child);
void (*process_exit)(struct proc *p);
int (*configure_counter)(struct proc *p, int ctr, struct pmc_counter_cfg *cfg);
int (*get_counter_val)(struct proc *p, int ctr, int flags, uint64_t *pval);
int (*counter_isconfigured)(struct proc *p, int ctr);
int (*counter_isrunning)(struct proc *p, int ctr);
int (*start_profiling)(int ctr, struct pmc_counter_cfg *cfg);
int (*stop_profiling)(int ctr);
int (*alloc_kernel_ctr)(int ctr, struct pmc_counter_cfg *cfg);
int (*free_kernel_ctr)(int ctr);
};
extern struct arm_pmc_funcs *arm_pmc;
#define pmc_md_fork(p1,p2) (arm_pmc->fork((p1),(p2)))
#define pmc_get_num_counters() (arm_pmc->num_counters())
#define pmc_get_counter_type(c) (arm_pmc->counter_type(c))
#define pmc_save_context(p) (arm_pmc->save_context(p))
#define pmc_restore_context(p) (arm_pmc->restore_context(p))
#define pmc_enable_counter(p,c) (arm_pmc->enable_counter((p),(c)))
#define pmc_disable_counter(p,c) (arm_pmc->disable_counter((p),(c)))
#define pmc_accumulate(p1,p2) (arm_pmc->accumulate((p1),(p2)))
#define pmc_process_exit(p1) (arm_pmc->process_exit(p))
#define pmc_counter_isconfigured(p,c) (arm_pmc->counter_isconfigured((p),(c)))
#define pmc_counter_isrunning(p,c) (arm_pmc->counter_isrunning((p),(c)))
#define pmc_start_profiling(c,f) (arm_pmc->start_profiling((c),(f)))
#define pmc_stop_profiling(c) (arm_pmc->stop_profiling((c)))
#define pmc_alloc_kernel_counter(c,f) (arm_pmc->alloc_kernel_ctr((c),(f)))
#define pmc_free_kernel_counter(c) (arm_pmc->free_kernel_ctr((c)))
#define pmc_configure_counter(p,c,f) \
(arm_pmc->configure_counter((p),(c),(f)))
#define pmc_get_counter_value(p,c,f,pv) \
(arm_pmc->get_counter_val((p),(c),(f),(pv)))
#define PMC_ENABLED(p) (p)->p_md.pmc_enabled
#endif /* defined(_KERNEL) */
#endif /* _ARM_PMC_H_ */

64
sys/arch/arm/include/proc.h
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@ -1,64 +0,0 @@
/* $NetBSD: proc.h,v 1.17 2014/02/24 16:57:57 christos Exp $ */
/*
* Copyright (c) 1994 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the RiscBSD team.
* 4. The name "RiscBSD" nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ARM_PROC_H_
#define _ARM_PROC_H_
/*
* Machine-dependent part of the proc structure for arm.
*/
struct trapframe;
struct lwp;
struct mdlwp {
struct trapframe *md_tf;
int md_flags;
};
/* Flags setttings for md_flags */
#define MDLWP_NOALIGNFLT 0x00000002 /* For EXEC_AOUT */
#define MDLWP_VFPINTR 0x00000004 /* VFP used in intr */
struct mdproc {
void (*md_syscall)(struct trapframe *, struct lwp *, uint32_t);
int pmc_enabled; /* bitfield of enabled counters */
void *pmc_state; /* port-specific pmc state */
char md_march[12]; /* machine arch of executable */
};
#define PROC0_MD_INITIALIZERS .p_md = { .md_march = MACHINE_ARCH },
#endif /* _ARM_PROC_H_ */

188
sys/arch/arm/include/profile.h
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@ -1,188 +0,0 @@
/* $NetBSD: profile.h,v 1.17 2015/01/11 20:52:57 joerg Exp $ */
/*
* Copyright (c) 2001 Ben Harris
* Copyright (c) 1995-1996 Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define _MCOUNT_DECL void _mcount
/*
* Cannot implement mcount in C as GCC will trash the ip register when it
* pushes a trapframe. Pity we cannot insert assembly before the function
* prologue.
*/
#define MCOUNT_ASM_NAME "__mcount"
#define PLTSYM
#if !defined(__ARM_EABI__)
#define MCOUNT \
__asm(".text"); \
__asm(".align 0"); \
__asm(".arm"); \
__asm(".type " MCOUNT_ASM_NAME ",%function"); \
__asm(".global " MCOUNT_ASM_NAME); \
__asm(MCOUNT_ASM_NAME ":"); \
/* \
* Preserve registers that are trashed during mcount \
*/ \
__asm("push {r0-r3, ip, lr}"); \
/* Check what mode we're in. EQ => 32, NE => 26 */ \
__asm("teq r0, r0"); \
__asm("teq pc, r15"); \
/* \
* find the return address for mcount, \
* and the return address for mcount's caller. \
* \
* frompcindex = pc pushed by call into self. \
*/ \
__asm("moveq r0, ip"); \
__asm("bicne r0, ip, #0xfc000003"); \
/* \
* selfpc = pc pushed by mcount call \
*/ \
__asm("moveq r1, lr"); \
__asm("bicne r1, lr, #0xfc000003"); \
/* \
* Call the real mcount code \
*/ \
__asm("bl " ___STRING(_C_LABEL(_mcount)) PLTSYM); \
/* \
* Restore registers that were trashed during mcount \
*/ \
__asm("pop {r0-r3, lr}"); \
__asm("pop {pc}"); \
__asm(".size " MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
#elif defined(__ARM_DWARF_EH__)
#define MCOUNT \
__asm(".text"); \
__asm(".align 0"); \
__asm(".arm"); \
__asm(".type " MCOUNT_ASM_NAME ",%function"); \
__asm(".global " MCOUNT_ASM_NAME); \
__asm(MCOUNT_ASM_NAME ":"); \
__asm(".cfi_startproc"); \
/* \
* Preserve registers that are trashed during mcount \
*/ \
__asm("push {r0-r3, ip, lr}"); \
__asm(".cfi_def_cfa_offset 24"); \
__asm(".cfi_offset 14, -4"); \
__asm(".cfi_offset 12, -8"); \
__asm(".cfi_offset 3, -12"); \
__asm(".cfi_offset 2, -16"); \
__asm(".cfi_offset 1, -20"); \
__asm(".cfi_offset 0, -24"); \
/* \
* find the return address for mcount, \
* and the return address for mcount's caller. \
* \
* frompcindex = pc pushed by call into self. \
*/ \
__asm("mov r0, ip"); \
/* \
* selfpc = pc pushed by mcount call \
*/ \
__asm("mov r1, lr"); \
/* \
* Call the real mcount code \
*/ \
__asm("bl " ___STRING(_C_LABEL(_mcount)) PLTSYM); \
/* \
* Restore registers that were trashed during mcount \
*/ \
__asm("pop {r0-r3, lr}"); \
__asm("pop {pc}"); \
__asm(".cfi_endproc"); \
__asm(".size " MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
#else
#define MCOUNT \
__asm(".text"); \
__asm(".align 0"); \
__asm(".arm"); \
__asm(".type " MCOUNT_ASM_NAME ",%function"); \
__asm(".global " MCOUNT_ASM_NAME); \
__asm(MCOUNT_ASM_NAME ":"); \
__asm(".fnstart"); \
__asm(".cfi_startproc"); \
/* \
* Preserve registers that are trashed during mcount \
*/ \
__asm("push {r0-r3, ip, lr}"); \
__asm(".save {r0-r3, lr}"); \
__asm(".cfi_def_cfa_offset 24"); \
__asm(".cfi_offset 14, -4"); \
__asm(".cfi_offset 12, -8"); \
__asm(".cfi_offset 3, -12"); \
__asm(".cfi_offset 2, -16"); \
__asm(".cfi_offset 1, -20"); \
__asm(".cfi_offset 0, -24"); \
/* \
* find the return address for mcount, \
* and the return address for mcount's caller. \
* \
* frompcindex = pc pushed by call into self. \
*/ \
__asm("mov r0, ip"); \
/* \
* selfpc = pc pushed by mcount call \
*/ \
__asm("mov r1, lr"); \
/* \
* Call the real mcount code \
*/ \
__asm("bl " ___STRING(_C_LABEL(_mcount)) PLTSYM); \
/* \
* Restore registers that were trashed during mcount \
*/ \
__asm("pop {r0-r3, lr}"); \
__asm("pop {pc}"); \
__asm(".cfi_endproc"); \
__asm(".fnend"); \
__asm(".size " MCOUNT_ASM_NAME ", .-" MCOUNT_ASM_NAME);
#endif
#ifdef _KERNEL
#ifdef __PROG26
extern int int_off_save(void);
extern void int_restore(int);
#define MCOUNT_ENTER (s = int_off_save())
#define MCOUNT_EXIT int_restore(s)
#else
#include <arm/cpufunc.h>
/*
* splhigh() and splx() are heavyweight, and call mcount(). Therefore
* we disabled interrupts (IRQ, but not FIQ) directly on the CPU.
*
* We're lucky that the CPSR and 's' both happen to be 'int's.
*/
#define MCOUNT_ENTER s = __set_cpsr_c(0x0080, 0x0080); /* kill IRQ */
#define MCOUNT_EXIT __set_cpsr_c(0xffffffff, s); /* restore old value */
#endif /* !acorn26 */
#endif /* _KERNEL */

62
sys/arch/arm/include/ptrace.h
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@ -1,62 +0,0 @@
/* $NetBSD: ptrace.h,v 1.8 2015/09/25 16:05:17 christos Exp $ */
/*
* Copyright (c) 1995 Frank Lancaster
* Copyright (c) 1995 Tools GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by TooLs GmbH.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* arm-dependent ptrace definitions
*/
#ifndef _KERNEL
#define PT_STEP (PT_FIRSTMACH + 0) /* Not implemented */
#endif
#define PT_GETREGS (PT_FIRSTMACH + 1)
#define PT_SETREGS (PT_FIRSTMACH + 2)
/* 3 and 4 are for FPE registers */
#define PT_GETFPREGS (PT_FIRSTMACH + 5)
#define PT_SETFPREGS (PT_FIRSTMACH + 6)
#define PT_MACHDEP_STRINGS \
"(unused)", \
"PT_GETREGS", \
"PT_SETREGS", \
"old PT_GETFPREGS", \
"old PT_SETFPREGS", \
"PT_GETFPREGS", \
"PT_SETFPREGS",
#include <machine/reg.h>
#define PTRACE_REG_PC(r) (r)->r_pc
#define PTRACE_REG_SET_PC(r, v) (r)->r_pc = (v)
#define PTRACE_REG_SP(r) (r)->r_sp
#define PTRACE_REG_INTRV(r) (r)->r[0]
#define PTRACE_BREAKPOINT ((const uint8_t[]) { 0xe7, 0xff, 0xff, 0xff })
#define PTRACE_BREAKPOINT_SIZE 4

60
sys/arch/arm/include/reg.h
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@ -1,60 +0,0 @@
/* $NetBSD: reg.h,v 1.6 2014/01/29 00:42:15 matt Exp $ */
/*
* Copyright (C) 1994, 1995 Frank Lancaster
* Copyright (C) 1994, 1995 TooLs GmbH.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by TooLs GmbH.
* 4. The name of TooLs GmbH may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* @(#)reg.h 5.5 (Berkeley) 1/18/91
*/
#ifndef _ARM_REG_H_
#define _ARM_REG_H_
struct reg {
unsigned int r[13];
unsigned int r_sp;
unsigned int r_lr;
unsigned int r_pc;
unsigned int r_cpsr;
};
struct vfpreg {
uint32_t vfp_fpexc;
uint32_t vfp_fpscr;
uint32_t vfp_fpinst;
uint32_t vfp_fpinst2;
uint64_t vfp_regs[33]; /* In case we need fstmx format. */
};
struct fpreg {
struct vfpreg fpr_vfp;
};
#endif /* !_ARM_REG_H_ */

61
sys/arch/arm/include/rwlock.h
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@ -1,61 +0,0 @@
/* $NetBSD: rwlock.h,v 1.9 2015/02/25 13:52:42 joerg Exp $ */
/*-
* Copyright (c) 2002, 2006 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe and Andrew Doran.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_RWLOCK_H_
#define _ARM_RWLOCK_H_
struct krwlock {
volatile uintptr_t rw_owner;
};
#ifdef __RWLOCK_PRIVATE
#define __HAVE_SIMPLE_RW_LOCKS 1
#ifdef MULTIPROCESSOR
#ifdef _ARM_ARCH_7
#define RW_RECEIVE(rw) __asm __volatile("dmb" ::: "memory")
#define RW_GIVE(rw) __asm __volatile("dsb" ::: "memory")
#else
#define RW_RECEIVE(rw) membar_consumer()
#define RW_GIVE(rw) membar_producer()
#endif
#else
#define RW_RECEIVE(rw) /* nothing */
#define RW_GIVE(rw) /* nothing */
#endif
#define RW_CAS(p, o, n) \
(atomic_cas_ulong((volatile unsigned long *)(p), (o), (n)) == (o))
#endif /* __RWLOCK_PRIVATE */
#endif /* _ARM_RWLOCK_H_ */

93
sys/arch/arm/include/setjmp.h
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@ -1,93 +0,0 @@
/* $NetBSD: setjmp.h,v 1.5 2013/01/11 13:56:32 matt Exp $ */
/*
* machine/setjmp.h: machine dependent setjmp-related information.
*/
#define _JBLEN 64 /* size, in longs, of a jmp_buf */
/*
* NOTE: The internal structure of a jmp_buf is *PRIVATE*
* This information is provided as there is software
* that fiddles with this with obtain the stack pointer
* (yes really ! and its commercial !).
*
* Description of the setjmp buffer
*
* word 0 magic number (dependent on creator)
* 13 fpscr vfp status control register
* 14 r4 register 4
* 15 r5 register 5
* 16 r6 register 6
* 17 r7 register 7
* 18 r8 register 8
* 19 r9 register 9
* 20 r10 register 10 (sl)
* 21 r11 register 11 (fp)
* 22 r12 register 12 (ip)
* 23 r13 register 13 (sp)
* 24 r14 register 14 (lr)
* 25 signal mask (dependent on magic)
* 26 (con't)
* 27 (con't)
* 28 (con't)
* 32-33 d8 (vfp register d8)
* 34-35 d9 (vfp register d9)
* 36-37 d10 (vfp register d10)
* 38-39 d11 (vfp register d11)
* 40-41 d12 (vfp register d12)
* 42-43 d13 (vfp register d13)
* 44-45 d14 (vfp register d14)
* 46-47 d15 (vfp register d15)
*
* The magic number number identifies the jmp_buf and
* how the buffer was created as well as providing
* a sanity check
*
* A side note I should mention - Please do not tamper
* with the floating point fields. While they are
* always saved and restored at the moment this cannot
* be garenteed especially if the compiler happens
* to be generating soft-float code so no fp
* registers will be used.
*
* Whilst this can be seen an encouraging people to
* use the setjmp buffer in this way I think that it
* is for the best then if changes occur compiles will
* break rather than just having new builds falling over
* mysteriously.
*/
#define _JB_MAGIC__SETJMP 0x4278f500
#define _JB_MAGIC_SETJMP 0x4278f501
#define _JB_MAGIC__SETJMP_VFP 0x4278f502
#define _JB_MAGIC_SETJMP_VFP 0x4278f503
/* Valid for all jmp_buf's */
#define _JB_MAGIC 0
#define _JB_REG_FPSCR 13
#define _JB_REG_R4 14
#define _JB_REG_R5 15
#define _JB_REG_R6 16
#define _JB_REG_R7 17
#define _JB_REG_R8 18
#define _JB_REG_R9 19
#define _JB_REG_R10 20
#define _JB_REG_R11 21
#define _JB_REG_R12 22
#define _JB_REG_R13 23
#define _JB_REG_R14 24
/* Only valid with the _JB_MAGIC_SETJMP magic */
#define _JB_SIGMASK 25
#define _JB_REG_D8 32
#define _JB_REG_D9 34
#define _JB_REG_D10 36
#define _JB_REG_D11 38
#define _JB_REG_D12 40
#define _JB_REG_D13 42
#define _JB_REG_D14 44
#define _JB_REG_D15 46

172
sys/arch/arm/include/signal.h
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@ -1,172 +0,0 @@
/* $NetBSD: signal.h,v 1.13 2014/01/29 00:42:15 matt Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* signal.h
*
* Architecture dependent signal types and structures
*
* Created : 30/09/94
*/
#ifndef _ARM_SIGNAL_H_
#define _ARM_SIGNAL_H_
#include <sys/featuretest.h>
#ifndef _LOCORE
typedef int sig_atomic_t;
#endif
#if defined(_NETBSD_SOURCE)
#ifndef _LOCORE
/*
* Information pushed on stack when a signal is delivered.
* This is used by the kernel to restore state following
* execution of the signal handler. It is also made available
* to the handler to allow it to restore state properly if
* a non-standard exit is performed.
*/
#if defined(__LIBC12_SOURCE__) || defined(_KERNEL)
struct sigcontext13 {
int sc_onstack; /* sigstack state to restore */
int sc_mask; /* signal mask to restore (old style) */
unsigned int sc_spsr;
unsigned int sc_r0;
unsigned int sc_r1;
unsigned int sc_r2;
unsigned int sc_r3;
unsigned int sc_r4;
unsigned int sc_r5;
unsigned int sc_r6;
unsigned int sc_r7;
unsigned int sc_r8;
unsigned int sc_r9;
unsigned int sc_r10;
unsigned int sc_r11;
unsigned int sc_r12;
unsigned int sc_usr_sp;
unsigned int sc_usr_lr;
unsigned int sc_svc_lr;
unsigned int sc_pc;
};
#endif /* __LIBC12_SOURCE__ || _KERNEL */
struct sigcontext {
int sc_onstack; /* sigstack state to restore */
int __sc_mask13; /* signal mask to restore (old style) */
unsigned int sc_spsr;
unsigned int sc_r0;
unsigned int sc_r1;
unsigned int sc_r2;
unsigned int sc_r3;
unsigned int sc_r4;
unsigned int sc_r5;
unsigned int sc_r6;
unsigned int sc_r7;
unsigned int sc_r8;
unsigned int sc_r9;
unsigned int sc_r10;
unsigned int sc_r11;
unsigned int sc_r12;
unsigned int sc_usr_sp;
unsigned int sc_usr_lr;
unsigned int sc_svc_lr;
unsigned int sc_pc;
sigset_t sc_mask; /* signal mask to restore (new style) */
#ifdef __minix
#define SC_MAGIC 0xc0ffee2
int sc_magic;
int sc_flags;
int trap_style;
#endif
};
#endif /* !_LOCORE */
/* Signals codes */
/*
* SIGFPE codes
*
* see ieeefp.h for definition of FP exception codes
*/
#define SIG_CODE_FPE_CODE_MASK 0x00000f00 /* Mask for exception code */
#define SIG_CODE_FPE_CODE_SHIFT 8 /* Shift for exception code */
#define SIG_CODE_FPE_TYPE_MASK 0x000000ff /* Mask for specific code */
/*
* SIGILL codes
*
* the signal code is the instruction that raised the signal
*/
/*
* SIGBUS and SIGSEGV codes
*
* The signal code is combination of the fault address and the fault code.
*
* The fault code is the coproc #15 fault status code
*
* The exception to this is a SIGBUS or SIGSEGV from a prefetch abort.
* In this case the fault status code is not valid so the TYPE_MASK
* should be treated as undefined (in practice it is the bottom 4 bits
* of the fault address).
*/
#define SIG_CODE_BUS_ADDR_MASK 0xfffffff0
#define SIG_CODE_BUS_TYPE_MASK 0x0000000f
#define SIG_CODE_SEGV_ADDR_MASK SIG_CODE_BUS_ADDR_MASK
#define SIG_CODE_SEGV_TYPE_MASK SIG_CODE_BUS_TYPE_MASK
#endif /* _NETBSD_SOURCE */
#if defined(__minix)
__BEGIN_DECLS
int sigreturn(struct sigcontext *_scp);
__END_DECLS
#endif /* defined(__minix) */
#endif /* !_ARM_SIGNAL_H_ */
/* End of signal.h */

59
sys/arch/arm/include/sljit_machdep.h
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@ -1,59 +0,0 @@
/* $NetBSD: sljit_machdep.h,v 1.1 2014/07/23 18:19:43 alnsn Exp $ */
/*-
* Copyright (c) 2014 Alexander Nasonov.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_SLJITARCH_H
#define _ARM_SLJITARCH_H
#include <sys/cdefs.h>
#ifdef _KERNEL
#include <machine/types.h>
#include <arm/cpufunc.h>
#else
#include <stddef.h>
#include <stdint.h>
#include <arm/sysarch.h>
#endif
#if defined(_ARM_ARCH_T2)
#define SLJIT_CONFIG_ARM_THUMB2 1
#elif defined(_ARM_ARCH_7)
#define SLJIT_CONFIG_ARM_V7 1
#else
#define SLJIT_CONFIG_ARM_V5 1
#endif
#ifdef _KERNEL
#define SLJIT_CACHE_FLUSH(from, to) \
cpu_icache_sync_range((vaddr_t)(from), (vsize_t)((to) - (from)))
#else
#define SLJIT_CACHE_FLUSH(from, to) \
(void)arm_sync_icache((uintptr_t)(from), (size_t)((to) - (from)))
#endif
#endif

22
sys/arch/arm/include/swi.h
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@ -1,22 +0,0 @@
/* $NetBSD: swi.h,v 1.1 2002/01/13 15:03:06 bjh21 Exp $ */
/*
* This file is in the Public Domain.
* Ben Harris, 2002.
*/
#ifndef _ARM_SWI_H_
#define _ARM_SWI_H_
#define SWI_OS_MASK 0xf00000
#define SWI_OS_RISCOS 0x000000
#define SWI_OS_RISCIX 0x800000
#define SWI_OS_LINUX 0x900000
#define SWI_OS_NETBSD 0xa00000
#define SWI_OS_ARM 0xf00000
#define SWI_IMB 0xf00000
#define SWI_IMBrange 0xf00001
#endif

85
sys/arch/arm/include/sysarch.h
View File

@ -1,85 +0,0 @@
/* $NetBSD: sysarch.h,v 1.12 2015/03/09 11:03:19 joerg Exp $ */
/*
* Copyright (c) 1996-1997 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ARM_SYSARCH_H_
#define _ARM_SYSARCH_H_
#include <sys/cdefs.h>
/*
* Pickup definition of size_t and uintptr_t
*/
#include <machine/ansi.h>
#include <sys/stdint.h>
#ifndef _KERNEL
#include <stdbool.h>
#endif
#ifdef _BSD_SIZE_T_
typedef _BSD_SIZE_T_ size_t;
#undef _BSD_SIZE_T_
#endif
/*
* Architecture specific syscalls (arm)
*/
#define ARM_SYNC_ICACHE 0
#define ARM_DRAIN_WRITEBUF 1
#define ARM_VFP_FPSCR 2
#define ARM_FPU_USED 3
struct arm_sync_icache_args {
uintptr_t addr; /* Virtual start address */
size_t len; /* Region size */
};
struct arm_vfp_fpscr_args {
uint32_t fpscr_clear; /* bits to clear */
uint32_t fpscr_set; /* bits to set */
};
struct arm_unaligned_faults_args {
bool enabled; /* unaligned faults are enabled */
};
#ifndef _KERNEL
__BEGIN_DECLS
int arm_sync_icache(uintptr_t, size_t);
int arm_drain_writebuf(void);
int sysarch(int, void *);
__END_DECLS
#endif
#endif /* !_ARM_SYSARCH_H_ */

77
sys/arch/arm/include/trap.h
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@ -1,77 +0,0 @@
/* $NetBSD: trap.h,v 1.9 2014/03/15 05:54:20 ozaki-r Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* trap.h
*
* Various trap definitions
*/
/*
* Instructions used for breakpoints.
*
* These are undefined instructions.
* Technically the userspace breakpoint could be a SWI but we want to
* keep this the same as IPKDB which needs an undefined instruction as
* a break point.
*
* Ideally ARM would define several standard instruction sequences for
* use as breakpoints.
*
* The BKPT instruction isn't much use to us, since its behaviour is
* unpredictable on ARMv3 and lower.
*
* The ARM ARM says that for maximum compatibility, we should use undefined
* instructions that look like 0x.7f...f. .
*/
#define GDB_BREAKPOINT 0xe6000011 /* Used by GDB 4.x */
#define IPKDB_BREAKPOINT_DEAD 0xe6000010 /* was used by IPKDB */
#define GDB5_BREAKPOINT 0xe7ffdefe /* Used by GDB 5.0 */
#define GDB_THUMB_BREAKPOINT 0xdefe /* Thumb in GDB */
#define KERNEL_BREAKPOINT 0xe7ffffff /* Used by DDB */
/*
* DTrace uses 0xe7fffef0 to 0xe7fffeff as breakpoints.
* The first byte is used to encode a cond value.
*/
#define DTRACE_BREAKPOINT 0xe7fffef0
#define DTRACE_BREAKPOINT_MASK 0xfffffff0
#define DTRACE_IS_BREAKPOINT(insn) ((insn & DTRACE_BREAKPOINT_MASK) == DTRACE_BREAKPOINT)
#define KBPT_ASM ".word 0xe7ffdefe"
#define USER_BREAKPOINT GDB_BREAKPOINT
/* End of trap.h */

105
sys/arch/arm/include/types.h
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@ -1,105 +0,0 @@
/* $NetBSD: types.h,v 1.30 2015/08/27 12:30:50 pooka Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)types.h 7.5 (Berkeley) 3/9/91
*/
#ifndef _ARM_TYPES_H_
#define _ARM_TYPES_H_
#include <sys/cdefs.h>
#include <sys/featuretest.h>
#include <arm/int_types.h>
#if defined(_KERNEL)
typedef struct label_t { /* Used by setjmp & longjmp */
int val[11];
} label_t;
#endif
/* NB: This should probably be if defined(_KERNEL) */
#if defined(_NETBSD_SOURCE)
typedef unsigned long paddr_t;
typedef unsigned long psize_t;
typedef unsigned long vaddr_t;
typedef unsigned long vsize_t;
#define PRIxPADDR "lx"
#define PRIxPSIZE "lx"
#define PRIuPSIZE "lu"
#define PRIxVADDR "lx"
#define PRIxVSIZE "lx"
#define PRIuVSIZE "lu"
#endif
typedef int register_t, register32_t;
#define PRIxREGISTER "x"
typedef unsigned long pmc_evid_t;
#define PMC_INVALID_EVID (-1)
typedef unsigned long pmc_ctr_t;
typedef unsigned short tlb_asid_t;
/*
* This should have always been an 8-bit type, but since it's been exposed
* to user-space, we don't want ABI breakage there.
*/
#if defined(_KERNEL)
typedef unsigned char __cpu_simple_lock_nv_t;
#else
typedef int __cpu_simple_lock_nv_t;
#endif /* _KERNEL */
#define __SIMPLELOCK_LOCKED 1
#define __SIMPLELOCK_UNLOCKED 0
#define __HAVE_SYSCALL_INTERN
#define __HAVE_NEW_STYLE_BUS_H
#define __HAVE_MINIMAL_EMUL
#define __HAVE_CPU_DATA_FIRST
#define __HAVE___LWP_GETPRIVATE_FAST
#define __HAVE_COMMON___TLS_GET_ADDR
#if !defined(__minix)
#define __HAVE_TLS_VARIANT_I
#endif /* !defined(__minix) */
#define __HAVE_OLD_DISKLABEL
#if defined(__ARM_EABI__) && defined(_ARM_ARCH_6)
#define __HAVE_ATOMIC64_OPS
#endif
#if defined(_KERNEL) || defined(_KMEMUSER)
#define PCU_FPU 0
#define PCU_UNIT_COUNT 1
#endif
#if defined(_KERNEL)
#define __HAVE_RAS
#endif
#endif /* _ARM_TYPES_H_ */

107
sys/arch/arm/include/undefined.h
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@ -1,107 +0,0 @@
/* $NetBSD: undefined.h,v 1.12 2009/03/14 14:45:55 dsl Exp $ */
/*
* Copyright (c) 1995-1996 Mark Brinicombe.
* Copyright (c) 1995 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* undefined.h
*
* Undefined instruction types, symbols and prototypes
*
* Created : 08/02/95
*/
#ifndef _ARM_UNDEFINED_H_
#define _ARM_UNDEFINED_H_
#ifdef _KERNEL
#include <sys/queue.h>
typedef int (*undef_handler_t)(unsigned int, unsigned int, trapframe_t *, int);
/*
* Enumeration of coprocessor numbers. Values may be duplicated
* (the iWMMX coprocessor clashes with the FPA, for example), but
* keep this table in numeric order.
*/
enum arm_coprocs {
FPA_COPROC = 1,
FPA_COPROC2 = 2,
VFP_COPROC = 10,
VFP_COPROC2 = 11,
DEBUG_COPROC = 14,
SYSTEM_COPROC = 15,
/*
*The following are not really co-processors, but are on the end
* of the unknown instruction table for each coproc.
*/
CORE_UNKNOWN_HANDLER = 16,
#ifdef THUMB_CODE
THUMB_UNKNOWN_HANDLER = 17,
#endif
NUM_UNKNOWN_HANDLERS /* Last entry */
};
/* Prototypes for undefined.c */
void *install_coproc_handler(int, undef_handler_t);
void remove_coproc_handler(void *);
void undefined_init(void);
/*
* XXX Stuff below here is for use before malloc() is available. Most code
* shouldn't use it.
*/
struct undefined_handler {
LIST_ENTRY(undefined_handler) uh_link;
undef_handler_t uh_handler;
};
/*
* Handlers installed using install_coproc_handler_static shouldn't be
* removed.
*/
void install_coproc_handler_static(int, struct undefined_handler *);
/* Calls up to undefined.c from trap handlers */
void undefinedinstruction(struct trapframe *);
#endif
/* End of undefined.h */
#endif /* _ARM_UNDEFINED_H_ */

115
sys/arch/arm/include/vfpreg.h
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@ -1,115 +0,0 @@
/* $NetBSD: vfpreg.h,v 1.14 2015/02/09 07:55:52 slp Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the company may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_VFPREG_H_
#define _ARM_VFPREG_H_
/* FPSID register */
#define VFP_FPSID_IMP_MSK 0xff000000 /* Implementer */
#define VFP_FPSID_IMP_ARM 0x41000000 /* Implementer: ARM */
#define VFP_FPSID_SW 0x00800000 /* VFP implemented in SW */
#define VFP_FPSID_FMT_MSK 0x00600000 /* FLDMX/FSTMX Format */
#define VFP_FPSID_FMT_1 0x00000000 /* Standard format 1 */
#define VFP_FPSID_FMT_2 0x00200000 /* Standard format 2 */
#define VFP_FPSID_FMT_WEIRD 0x00600000 /* Non-standard format */
#define VFP_FPSID_SP 0x00100000 /* Only single precision */
#define VFP_FPSID_ARCH_MSK 0x000f0000 /* Architecture */
#define VFP_FPSID_ARCH_V1 0x00000000 /* Arch VFPv1 */
#define VFP_FPSID_ARCH_V2 0x00010000 /* Arch VFPv2 */
#define VFP_FPSID_ARCH_V3_2 0x00020000 /* Arch VFPv3 (subarch v2) */
#define VFP_FPSID_ARCH_V3 0x00030000 /* Arch VFPv3 (no subarch) */
#define VFP_FPSID_ARCH_V3_3 0x00040000 /* Arch VFPv3 (subarch v3) */
#define VFP_FPSID_PART_MSK 0x0000ff00 /* Part number */
#define VFP_FPSID_PART_VFP10 0x00001000 /* VFP10 */
#define VFP_FPSID_PART_VFP11 0x00002000 /* VFP11 */
#define VFP_FPSID_PART_VFP30 0x00003000 /* VFP30 */
#define VFP_FPSID_VAR_MSK 0x000000f0 /* Variant */
#define VFP_FPSID_VAR_ARM10 0x000000a0 /* Variant ARM10 */
#define VFP_FPSID_VAR_ARM11 0x000000b0 /* Variant ARM11 */
#define VFP_FPSID_REV_MSK 0x0000000f /* Revision */
#define FPU_VFP10_ARM10E 0x410001a0 /* Really a VFPv2 part */
#define FPU_VFP11_ARM11 0x410120b0
#define FPU_VFP_CORTEXA5 0x41023050
#define FPU_VFP_CORTEXA7 0x41023070
#define FPU_VFP_CORTEXA8 0x410330c0
#define FPU_VFP_CORTEXA9 0x41033090
#define FPU_VFP_CORTEXA15 0x410330f0
#define FPU_VFP_CORTEXA15_QEMU 0x410430f0
#define FPU_VFP_MV88SV58XX 0x56022090
#define VFP_FPEXC_EX 0x80000000 /* EXception status bit */
#define VFP_FPEXC_EN 0x40000000 /* VFP Enable bit */
#define VFP_FPEXC_DEX 0x20000000 /* Defined sync EXception bit */
#define VFP_FPEXC_FP2V 0x10000000 /* FPinst2 instruction Valid */
#define VFP_FPEXC_VV 0x08000000 /* Vecitr Valid */
#define VFP_FPEXC_TFV 0x04000000 /* Trapped Fault Valid */
#define VFP_FPEXC_VECITR 0x00000700 /* VECtor ITeRation count */
#define VFP_FPEXC_IDF 0x00000080 /* Input Denormal flag */
#define VFP_FPEXC_IXF 0x00000010 /* Potential inexact flag */
#define VFP_FPEXC_UFF 0x00000008 /* Potential underflow flag */
#define VFP_FPEXC_OFF 0x00000004 /* Potential overflow flag */
#define VFP_FPEXC_DZF 0x00000002 /* Potential DivByZero flag */
#define VFP_FPEXC_IOF 0x00000001 /* Potential inv. op. flag */
#define VFP_FPEXC_FSUM 0x000000ff /* all flag bits */
#define VFP_FPSCR_N 0x80000000 /* set if compare <= result */
#define VFP_FPSCR_Z 0x40000000 /* set if compare = result */
#define VFP_FPSCR_C 0x20000000 /* set if compare (=,>=,UNORD) result */
#define VFP_FPSCR_V 0x10000000 /* set if compare UNORD result */
#define VFP_FPSCR_QC 0x08000000 /* Cumulative saturation (SIMD) */
#define VFP_FPSCR_AHP 0x04000000 /* Alternative Half-Precision */
#define VFP_FPSCR_DN 0x02000000 /* Default NaN mode */
#define VFP_FPSCR_FZ 0x01000000 /* Flush-to-zero mode */
#define VFP_FPSCR_RMODE 0x00c00000 /* Rounding Mode */
#define VFP_FPSCR_RZ 0x00c00000 /* round towards zero (RZ) */
#define VFP_FPSCR_RM 0x00800000 /* round towards +INF (RP) */
#define VFP_FPSCR_RP 0x00400000 /* round towards -INF (RM) */
#define VFP_FPSCR_RN 0x00000000 /* round to nearest (RN) */
#define VFP_FPSCR_STRIDE 0x00300000 /* Vector Stride */
#define VFP_FPSCR_LEN 0x00070000 /* Vector Length */
#define VFP_FPSCR_IDE 0x00008000 /* Inout Subnormal Exception Enable */
#define VFP_FPSCR_ESUM 0x00001f00 /* IXE|UFE|OFE|DZE|IOE */
#define VFP_FPSCR_IXE 0x00001000 /* Inexact Exception Enable */
#define VFP_FPSCR_UFE 0x00000800 /* Underflow Exception Enable */
#define VFP_FPSCR_OFE 0x00000400 /* Overflow Exception Enable */
#define VFP_FPSCR_DZE 0x00000200 /* DivByZero Exception Enable */
#define VFP_FPSCR_IOE 0x00000100 /* Invalid Operation Cumulative Flag */
#define VFP_FPSCR_IDC 0x00000080 /* Input Subnormal Cumlative Flag */
#define VFP_FPSCR_CSUM 0x0000001f /* IXC|UFC|OFC|DZC|IOC */
#define VFP_FPSCR_IXC 0x00000010 /* Inexact Cumulative Flag */
#define VFP_FPSCR_UFC 0x00000008 /* Underflow Cumulative Flag */
#define VFP_FPSCR_OFC 0x00000004 /* Overflow Cumulative Flag */
#define VFP_FPSCR_DZC 0x00000002 /* DivByZero Cumulative Flag */
#define VFP_FPSCR_IOC 0x00000001 /* Invalid Operation Cumulative Flag */
#endif /* _ARM_VFPREG_H_ */

3
sys/arch/arm/include/vmparam.h
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@ -1,3 +0,0 @@
/* $NetBSD: vmparam.h,v 1.3 2013/05/01 12:00:51 matt Exp $ */
#include <arm/arm32/vmparam.h>

75
sys/arch/arm/include/wchar_limits.h
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@ -1,75 +0,0 @@
/* $NetBSD: wchar_limits.h,v 1.4 2013/01/24 10:17:00 matt Exp $ */
/*-
* Copyright (c) 2004 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_WCHAR_LIMITS_H_
#define _ARM_WCHAR_LIMITS_H_
/*
* 7.18.3 Limits of other integer types
*/
/* limits of wchar_t */
#ifdef __WCHAR_MIN__
#define WCHAR_MIN __WCHAR_MIN__ /* wchar_t */
#elif __WCHAR_UNSIGNED__
#define WCHAR_MIN 0U /* wchar_t */
#else
#define WCHAR_MIN (-0x7fffffff-1) /* wchar_t */
#endif
#ifdef __WCHAR_MAX__
#define WCHAR_MAX __WCHAR_MAX__ /* wchar_t */
#elif __WCHAR_UNSIGNED__
#define WCHAR_MAX 0xffffffffU /* wchar_t */
#else
#define WCHAR_MAX 0x7fffffff /* wchar_t */
#endif
/* limits of wint_t */
#ifdef __WINT_MIN__
#define WINT_MIN __WINT_MIN__ /* wint_t */
#elif __WINT_UNSIGNED__
#define WINT_MIN 0U /* wint_t */
#else
#define WINT_MIN (-0x7fffffff-1) /* wint_t */
#endif
#ifdef __WINT_MAX__
#define WINT_MAX __WINT_MAX__ /* wint_t */
#elif __WINT_UNSIGNED__
#define WINT_MAX 0xffffffffU /* wint_t */
#else
#define WINT_MAX 0x7fffffff /* wint_t */
#endif
#endif /* !_ARM_WCHAR_LIMITS_H_ */

95
sys/arch/evbarm/Makefile
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@ -1,95 +0,0 @@
# $NetBSD: Makefile,v 1.10 2015/01/23 12:34:09 hkenken Exp $
# Makefile for evbarm tags file and boot blocks
# Find where ARM source files are for inclusion in tags
.include <../arm/Makefile.inc>
TEVBARM= ${SYSDIR}/arch/evbarm/tags
SEVBARM= ${SYSDIR}/arch/evbarm/adi_brh/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/armadillo/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/beagle/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/cp3100/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/dev/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/devkit8000/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/evbarm/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/g42xxeb/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/gemini/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/gumstix/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/hdl_g/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/ifpga/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/imx31/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/include/*.h
SEVBARM+= ${SYSDIR}/arch/evbarm/integrator/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/iq31244/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/iq80310/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/iq80321/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/ixdp425/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/ixm1200/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/lubbock/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/marvell/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/mini2440/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/mpcsa/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/netwalker/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/npwr_fc/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/nslu2/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/rpi/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/osk5912/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/smdk2xx0/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/tisdp24xx/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/tsarm/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/viper/*.[ch]
SEVBARM+= ${SYSDIR}/arch/evbarm/zynq/*.[ch]
SEVBARM+= ${SYSDIR}/arch/arm/xscale/*.[ch]
AEVBARM= ${SYSDIR}/arch/evbarm/adi_brh/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/armadillo/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/beagle/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/g42xxeb/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/gemini/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/gumstix/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/hdl_g/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/imx31/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/ixdp425/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/ixm1200/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/lubbock/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/marvell/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/mini2440/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/mpcsa/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/netwalker/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/nslu2/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/rpi/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/smdk2xx0/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/tisdp24xx/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/tsarm/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/viper/*.S
AEVBARM+= ${SYSDIR}/arch/arm/xscale/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/integrator/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/iq80310/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/iq80321/*.S
AEVBARM+= ${SYSDIR}/arch/evbarm/zynq/*.S
# Directories in which to place tags links
DEVBARM= include
.if !defined(__MINIX)
.include "../../kern/Make.tags.inc"
tags:
-rm -f ${TEVBARM}
-echo ${SEVBARM} ${SARM} | xargs ctags -wadtf ${TEVBARM}
-${FINDCOMM} | xargs ctags -wadtf ${TEVBARM}
egrep "^ENTRY(.*)|^ALTENTRY(.*)" ${AEVBARM} ${AARM} | \
${TOOL_SED} -e \
"s;\([^:]*\):\([^(]*\)(\([^, )]*\)\(.*\);\3 \1 /^\2(\3\4$$/;" \
>> ${TEVBARM}
sort -o ${TEVBARM} ${TEVBARM}
links:
-for i in ${DEVBARM}; do \
cd $$i && rm -f tags; ln -s ../tags tags; done
.endif # !defined(__MINIX)
SUBDIR= include
.include <bsd.subdir.mk>

7
sys/arch/evbarm/include/Makefile
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@ -1,7 +0,0 @@
# $NetBSD: Makefile,v 1.22 2014/07/23 18:19:43 alnsn Exp $
INCSDIR= /usr/include/evbarm
INCS= sljit_machdep.h
.include "../../arm/include/Makefile.common"

3
sys/arch/evbarm/include/ansi.h
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@ -1,3 +0,0 @@
/* $NetBSD: ansi.h,v 1.1 2001/11/25 15:56:03 thorpej Exp $ */
#include <arm/ansi.h>

3
sys/arch/evbarm/include/aout_machdep.h
View File

@ -1,3 +0,0 @@
/* $NetBSD: aout_machdep.h,v 1.1 2001/11/25 15:56:03 thorpej Exp $ */
#include <arm/aout_machdep.h>

3
sys/arch/evbarm/include/asm.h
View File

@ -1,3 +0,0 @@
/* $NetBSD: asm.h,v 1.1 2001/11/25 15:56:03 thorpej Exp $ */
#include <arm/asm.h>

1
sys/arch/evbarm/include/atomic.h
View File

@ -1 +0,0 @@
#include <arm/atomic.h>

44
sys/arch/evbarm/include/autoconf.h
View File

@ -1,44 +0,0 @@
/* $NetBSD: autoconf.h,v 1.8 2014/05/10 20:12:16 reinoud Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Matt Thomas <matt@3am-software.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _EVBARM_AUTOCONF_H_
#define _EVBARM_AUTOCONF_H_
#ifndef _ARM_MAINBUS_MAINBUS_H_
struct mainbus_attach_args {
const char *ma_name;
};
#endif
extern void (*evbarm_device_register)(device_t, void *);
extern void (*evbarm_device_register_post_config)(device_t, void *);
#endif /* _EVBARM_AUTOCONF_H_ */

61
sys/arch/evbarm/include/bootconfig.h
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@ -1,61 +0,0 @@
/* $NetBSD: bootconfig.h,v 1.6 2006/02/06 14:03:22 hamajima Exp $ */
/*
* Copyright (c) 1994 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <arm/bootconfig.h>
typedef struct _PhysMem {
u_int address;
u_int pages;
u_int flags;
#define BOOT_DRAM_CAN_DMA 1 /* Can DMA direct to this memory. */
#define BOOT_DRAM_PREFER 2 /* UVM should prefer this memory. */
} PhysMem;
#ifndef DRAM_BLOCKS
#define DRAM_BLOCKS 2
#endif
typedef struct _BootConfig {
u_int dramblocks;
PhysMem dram[DRAM_BLOCKS];
} BootConfig;
extern BootConfig bootconfig;
#define MAX_BOOT_STRING 255
/* End of bootconfig.h */

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