Update vt6105 and submit ip1000 driver code
This commit is contained in:
Jia-Ju Bai
parent
b193d0299c
commit
1df53b6cc9
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@ -1,4 +1,4 @@
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# Makefile for the ip1000 Ethernet drivers
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# Makefile for the Ethernet drivers
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PROG= ip1000
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SRCS= ip1000.c
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@ -9,6 +9,10 @@ Maybe the Ethernet cards of other PCI numbers for IC Plus can be supported.
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Revision 1.0 2016/11/02
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Authored by Jia-Ju Bai <baijiaju1990@163.com>
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Revision 1.1 2016/11/12
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Modification: Remove and rewrite Linux-derived code
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Authored by Jia-Ju Bai <baijiaju1990@163.com>
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Something can be improved:
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1. Ethernet address can not be modified at present.
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2. Dump interfaces are not provided.
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84
minix/drivers/net/ip1000/io.h
Normal file
84
minix/drivers/net/ip1000/io.h
Normal file
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@ -0,0 +1,84 @@
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#ifndef _IO_H
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#define _IO_H
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#include <sys/types.h>
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#include <minix/syslib.h>
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#include "ip1000.h"
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/* I/O function */
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static u8_t my_inb(u32_t port) {
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u32_t value;
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int r;
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#ifdef DMA_REG_MODE
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value = *(u8_t *)(port);
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#else
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if ((r = sys_inb(port, &value)) != OK)
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printf("ip1000: sys_inb failed: %d\n", r);
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#endif
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return (u8_t)value;
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}
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#define ic_in8(port, offset) (my_inb((port) + (offset)))
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static u16_t my_inw(u32_t port) {
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u32_t value;
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int r;
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#ifdef DMA_REG_MODE
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value = *(u16_t *)(port);
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#else
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if ((r = sys_inw(port, &value)) != OK)
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printf("ip1000: sys_inw failed: %d\n", r);
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#endif
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return (u16_t)value;
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}
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#define ic_in16(port, offset) (my_inw((port) + (offset)))
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static u32_t my_inl(u32_t port) {
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u32_t value;
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int r;
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#ifdef DMA_REG_MODE
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value = *(u32_t *)(port);
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#else
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if ((r = sys_inl(port, &value)) != OK)
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printf("ip1000: sys_inl failed: %d\n", r);
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#endif
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return value;
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}
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#define ic_in32(port, offset) (my_inl((port) + (offset)))
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static void my_outb(u32_t port, u8_t value) {
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int r;
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#ifdef DMA_REG_MODE
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*(u8_t *)(port) = value;
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#else
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if ((r = sys_outb(port, value)) != OK)
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printf("ip1000: sys_outb failed: %d\n", r);
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#endif
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}
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#define ic_out8(port, offset, value) \
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(my_outb(((port) + (offset)), (value)))
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static void my_outw(u32_t port, u16_t value) {
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int r;
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#ifdef DMA_REG_MODE
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*(u16_t *)(port) = value;
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#else
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if ((r = sys_outw(port, value)) != OK)
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printf("ip1000: sys_outw failed: %d\n", r);
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#endif
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}
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#define ic_out16(port, offset, value) \
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(my_outw(((port) + (offset)), (value)))
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static void my_outl(u16_t port, u32_t value) {
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int r;
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#ifdef DMA_REG_MODE
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*(u32_t *)(port) = value;
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#else
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if ((r = sys_outl(port, value)) != OK)
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printf("ip1000: sys_outl failed: %d\n", r);
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#endif
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}
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#define ic_out32(port, offset, value) \
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(my_outl(((port) + (offset)), (value)))
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#endif
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File diff suppressed because it is too large
Load Diff
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@ -1,262 +1,193 @@
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#ifndef _ic_H
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#define _ic_H
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#include <minix/drivers.h>
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#include <minix/netdriver.h>
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#include <machine/pci.h>
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#include <minix/ds.h>
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#include <assert.h>
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/* PCI Register */
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#define IC_PCI_VID 0x00 /* Vendor ID */
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#define IC_PCI_DID 0x02 /* Device ID */
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#define IC_PCI_CMD 0x04 /* Command */
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#define IC_PCI_STS 0x06 /* Status */
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#define IC_PCI_RID 0x08 /* Revision ID */
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#define IC_PCI_CC 0x09 /* Class Code */
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#define IC_PCI_CLS 0x0c /* Cache Line Size */
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#define IC_PCI_LT 0x0d /* Latency Timer */
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#define IC_PCI_HT 0x0e /* Header Type */
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/* ======= General Parameter ======= */
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/* Global configure */
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#define DESC_BASE64
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/* Internal Register */
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#define IC_REG_DMA_CTRL 0x00 /* DMA Control */
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#define IC_REG_TX_DESC0 0x10 /* Tx Descriptor Address 0 */
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#define IC_REG_TX_DESC1 0x14 /* Tx Descriptor Address 1 */
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#define IC_REG_TX_DMA_BTH 0x18 /* Tx DMA Burst Threshold */
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#define IC_REG_TX_DMA_UTH 0x19 /* Tx DMA Urgent Threshold */
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#define IC_REG_TX_DMA_PERIOD 0x1a /* Tx DMA Poll Period */
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#define IC_REG_RX_DESC0 0x1c /* Rx Descriptor Address 0 */
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#define IC_REG_RX_DESC1 0x20 /* Rx Descriptor Address 1 */
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#define IC_REG_RX_DMA_BTH 0x24 /* Rx DMA Burst Threshold */
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#define IC_REG_RX_DMA_UTH 0x25 /* Rx DMA Urgent Threshold */
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#define IC_REG_RX_DMA_PERIOD 0x26 /* Rx DMA Poll Period */
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#define IC_REG_DEBUG_CTRL 0x2c /* Debug Control */
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#define IC_REG_ASIC_CTRL 0x30 /* Main Control */
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#define IC_REG_FLOW_OFF_TH 0x3c /* Flow Off Threshold */
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#define IC_REG_FLOW_ON_TH 0x3e /* Flow On Threshold */
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#define IC_REG_EEPROM_DATA 0x48 /* EEPROM Data */
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#define IC_REG_EEPROM_CTRL 0x4a /* EEPROM Control */
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#define IC_REG_INTR_STS_ACK 0x5a /* Interrupt Status Acknowlege */
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#define IC_REG_INTR_ENA 0x5c /* Interrupt Enable */
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#define IC_REG_INTR_STS 0x5e /* Interrupt Status */
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#define IC_REG_TX_STS 0x60 /* Tx Status */
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#define IC_REG_MAC_CTRL 0x6c /* MAC Control */
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#define IC_REG_PHY_SET 0x75 /* Physical Register Set */
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#define IC_REG_PHY_CTRL 0x76 /* Physical Register Control */
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#define IC_REG_STA_ADDR0 0x78 /* Station Address 0 */
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#define IC_REG_STA_ADDR1 0x7a /* Station Address 1 */
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#define IC_REG_STA_ADDR2 0x7c /* Station Address 2 */
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#define IC_REG_MAX_FRAME 0x86 /* Max Frame Size */
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#define IC_REG_RX_MODE 0x88 /* Receive Mode */
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#define IC_REG_HASH_TLB0 0x8c /* Hash Table 0 */
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#define IC_REG_HASH_TLB1 0x90 /* Hash Table 1 */
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/* Rx/Tx buffer parameter */
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#define RX_BUF_SIZE 1536
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#define TX_BUF_SIZE 1536
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#define RX_DESC_NUM 64
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#define TX_DESC_NUM 64
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/* Receive Configure Mode */
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#define IC_RM_UNICAST 0x01
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#define IC_RM_MULTICAST 0x02
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#define IC_RM_BROADCAST 0x04
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#define IC_RM_ALLFRAMES 0x08
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/* Key internal register */
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#define REG_RCR 0x88
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#define REG_ISR 0x5a
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#define REG_IMR 0x5c
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#define REG_RX_DESC_BASEL 0x1c
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#define REG_TX_DESC_BASEL 0x10
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/* Interrupt Enable/Status Command */
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#define IC_IR_IRQ_STS 0x0001
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#define IC_IR_HOST_ERR 0x0002
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#define IC_IR_TX_DONE 0x0004
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#define IC_IR_MAC_CTRL 0x0008
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#define IC_IR_RX_DONE 0x0010
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#define IC_IR_RX_EARLY 0x0020
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#define IC_IR_REQUESTED 0x0040
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#define IC_IR_UPDATE_STS 0x0080
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#define IC_IR_LINK_EVENT 0x0100
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#define IC_IR_TX_DMA_DONE 0x0200
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#define IC_IR_RX_DMA_DONE 0x0400
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#define IC_IR_RFD_END 0x0800
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#define IC_IR_RX_DMA_PRIOR 0x1000
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#define IC_IR_COMMON (IC_IR_HOST_ERR | IC_IR_TX_DMA_DONE | \
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IC_IR_TX_DONE | IC_IR_REQUESTED | \
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IC_IR_UPDATE_STS | IC_IR_LINK_EVENT | \
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IC_IR_RX_DMA_DONE | IC_IR_RX_DONE | \
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IC_IR_RX_DMA_PRIOR)
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#ifdef DESC_BASE_DMA64
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#define REG_RX_DESC_BASEU 0x20
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#define REG_TX_DESC_BASEU 0x14
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#endif
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/* ASIC Control Register Command */
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#define IC_AC_SPEED10 0x00000010
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#define IC_AC_SPEED100 0x00000020
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#define IC_AC_SPEED1000 0x00000040
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#define IC_AC_LED_MODE 0x00004000
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#define IC_AC_GB_RESET 0x00010000
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#define IC_AC_RX_RESET 0x00020000
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#define IC_AC_TX_RESET 0x00040000
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#define IC_AC_DMA 0x00080000
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#define IC_AC_FIFO 0x00100000
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#define IC_AC_NETWORK 0x00200000
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#define IC_AC_HOST 0x00400000
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#define IC_AC_AUTO_INIT 0x00800000
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#define IC_AC_INTR_IRQ 0x02000000
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#define IC_AC_RESET_BUSY 0x04000000
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#define IC_AC_LED_SPEED 0x08000000
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#define IC_AC_LED_MODE_BIT1 0x20000000
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#define IC_AC_RESET_ALL (IC_AC_GB_RESET | IC_AC_RX_RESET | \
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IC_AC_TX_RESET | IC_AC_DMA | IC_AC_FIFO | \
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IC_AC_NETWORK | IC_AC_HOST | IC_AC_AUTO_INIT)
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/* Key internal register width */
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#define WIDTH_REG_RCR 8
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#define WIDTH_REG_ISR 16
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#define WIDTH_REG_IMR 16
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/* EEPROM Control Command */
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#define IC_EC_ADDDR 0x83ff
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#define IC_EC_OPCODE 0x00ff
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#define IC_EC_WRITE 0x0100
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#define IC_EC_READ 0x0200
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#define IC_EC_ERASE 0x0300
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#define IC_EC_BUSY 0x8000
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/* Interrupt statu and command */
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#define INTR_ISR_ERR 0x0002
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#define INTR_ISR_LINK_EVENT 0x0100
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#define INTR_ISR_RX_DONE 0x0400
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#define INTR_ISR_TX_DONE 0x0200
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#define INTR_ISR_CLEAR 0x0000
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#define INTR_IMR_ENABLE 0x17f6
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#define INTR_IMR_DISABLE 0x0000
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/* MAC Control Command */
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#define IC_MC_DUPLEX_SEL 0x00000020
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#define IC_MC_TX_FC_ENA 0x00000080
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#define IC_MC_RX_FC_ENA 0x00000100
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#define IC_MC_STAT_DISABLE 0x00400000
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#define IC_MC_TX_ENABLE 0x01000000
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#define IC_MC_TX_DISABLE 0x02000000
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#define IC_MC_TX_ENABLED 0x04000000
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#define IC_MC_RX_ENABLE 0x08000000
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#define IC_MC_RX_DISABLE 0x10000000
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#define IC_MC_RX_ENABLED 0x20000000
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#define IC_MC_PAUSED 0x40000000
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/* Descriptor status */
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#define DESC_STATUS_RX_RECV_ERR 0x00000000003f0000ULL
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#define DESC_STATUS_RX_RECV_CLEAR 0x0000000000000000ULL
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#define DESC_STATUS_TX_SEND_ERR 0x0000000000000000ULL
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#define DESC_STATUS_TX_SEND_CLEAR 0x0000000000000000ULL
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/* DMA Control Command */
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#define IC_DC_TX_POLL 0x00001000
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/* Rx mode */
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#define RCR_UNICAST 0x01
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#define RCR_MULTICAST 0x02
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#define RCR_BROADCAST 0x04
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/* Physical Control Command */
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#define IC_PC_MGMTCLK_LO 0x00
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#define IC_PC_MGMTCLK_HI 0x01
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#define IC_PC_MGMTDATA 0x02
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#define IC_PC_MGMTDIR 0x04
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#define IC_PC_DUPLEX_POLARITY 0x08
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#define IC_PC_DUPLEX_STS 0x10
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#define IC_PC_LINK_POLARITY 0x20
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#define IC_PC_LINK_SPEED 0xc0
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#define IC_PC_LINK_SPEED10 0x40
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#define IC_PC_LINK_SPEED100 0x80
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#define IC_PC_LINK_SPEED1000 0xc0
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/* Link status */
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#define LINK_UP 1
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#define LINK_DOWN 0
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#define LINK_UNKNOWN -1
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/* Tx Status */
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#define IC_TS_TX_ERR 0x00000001
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#define IC_TS_TX_COLLISION 0x00000004
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#define IC_TS_TX_MAX_COLL 0x00000008
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#define IC_TS_TX_UNDERRUN 0x00000010
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#define IC_TS_TX_IND_REQD 0x00000040
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#define IC_TS_TX_DONE 0x00000080
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#define IC_TS_TX_FRAMEID 0xffff0000
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/* Basic Rx/Tx parameters */
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#define RX_BUF_SIZE 1536
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#define TX_BUF_SIZE 1536
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#define RX_DESC_NUM 256
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#define TX_DESC_NUM 256
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/* Tx Frame Status */
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#define IC_TFS_FRAMEID 0x000000000000ffffULL
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#define IC_TFS_WORD_ALIGN 0x0000000000030000ULL
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#define IC_TFS_TCP_CHECKSUM 0x0000000000040000ULL
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#define IC_TFS_UDP_CHECKSUM 0x0000000000080000ULL
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#define IC_TFS_IP_CHECKSUM 0x0000000000100000ULL
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#define IC_TFS_FRAG_COUNT 0x000000000f000000ULL
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#define IC_TFS_WORD_ALIGN 0x0000000000030000ULL
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#define IC_TFS_TX_DMA_INDICATE 0x0000000000800000ULL
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#define IC_TFS_TFD_DONE 0x0000000080000000ULL
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/* ======= Self-defined Parameter ======= */
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#define RFI_FRAG_LEN 0xffff000000000000ULL
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#define RFS_FRAME_LEN 0x000000000000ffffULL
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#define RFS_FRAME_START 0x0000000020000000ULL
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#define RFS_FRAME_END 0x0000000040000000ULL
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#define RFS_RFD_DONE 0x0000000080000000ULL
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#define RFS_NORMAL (RFS_RFD_DONE | RFS_FRAME_START | RFS_FRAME_END)
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/* Tx Frame Information */
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#define IC_TFI_FRAG_ADDR 0x000000ffffffffffULL
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#define IC_TFI_FRAG_LEN 0xffff000000000000ULL
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#define TFI_FRAG_LEN 0xffff000000000000ULL
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#define TFS_FRAMEID 0x000000000000ffffULL
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#define TFS_WORD_ALIGN 0x0000000000030000ULL
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#define TFS_TX_DMA_INDICATE 0x0000000000800000ULL
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#define TFS_FRAG_COUNT 0x000000000f000000ULL
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#define TFS_TFD_DONE 0x0000000080000000ULL
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/* Rx Frame Status */
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#define IC_RFS_FRAME_LEN 0x000000000000ffffULL
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#define IC_RFS_OVERRUN 0x0000000000010000ULL
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#define IC_RFS_RUNT 0x0000000000020000ULL
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#define IC_RFS_ALIGN_ERR 0x0000000000040000ULL
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#define IC_RFS_FCS_ERR 0x0000000000080000ULL
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#define IC_RFS_OVERSIZE 0x0000000000100000ULL
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#define IC_RFS_LEN_ERR 0x0000000000200000ULL
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#define IC_RFS_VLAN_DETECT 0x0000000000400000ULL
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#define IC_RFS_TCP_DETECT 0x0000000000800000ULL
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#define IC_RFS_TCP_ERR 0x0000000001000000ULL
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#define IC_RFS_UCP_DETECT 0x0000000002000000ULL
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#define IC_RFS_UCP_ERR 0x0000000004000000ULL
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#define IC_RFS_IP_DETECT 0x0000000008000000ULL
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#define IC_RFS_IP_ERR 0x0000000010000000ULL
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#define IC_RFS_FRAME_START 0x0000000020000000ULL
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#define IC_RFS_FRAME_END 0x0000000040000000ULL
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#define IC_RFS_RFD_DONE 0x0000000080000000ULL
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#define IC_RFS_TCI 0x0000ffff00000000ULL
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#define IC_RFS_NORMAL (IC_RFS_RFD_DONE | IC_RFS_FRAME_START | \
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IC_RFS_FRAME_END)
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#define IC_RFS_ALL_ERR (IC_RFS_OVERRUN | IC_RFS_RUNT | \
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IC_RFS_ALIGN_ERR | IC_RFS_FCS_ERR | \
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IC_RFS_OVERSIZE | IC_RFS_LEN_ERR)
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#define REG_DMA_CTRL 0x00
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#define REG_TX_DMA_BTH 0x18
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#define REG_TX_DMA_UTH 0x19
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#define REG_TX_DMA_PERIOD 0x1a
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#define REG_RX_DMA_BTH 0x24
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#define REG_RX_DMA_UTH 0x25
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#define REG_RX_DMA_PERIOD 0x26
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#define REG_ASIC_CTRL 0x30
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#define REG_FLOW_OFF_TH 0x3c
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#define REG_FLOW_ON_TH 0x3e
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#define REG_EEPROM_DATA 0x48
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#define REG_EEPROM_CTRL 0x4a
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#define REG_MAC_CTRL 0x6c
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#define REG_PHY_SET 0x75
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#define REG_PHY_CTRL 0x76
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#define REG_STA_ADDR0 0x78
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#define REG_STA_ADDR1 0x7a
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#define REG_STA_ADDR2 0x7c
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#define REG_MAX_FRAME 0x86
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/* Rx Frame Information */
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#define IC_RFI_FRAG_ADDR 0x000000ffffffffffULL
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#define IC_RFI_FRAG_LEN 0xffff000000000000ULL
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#define AC_LED_MODE 0x00004000
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#define AC_GB_RESET 0x00010000
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#define AC_RX_RESET 0x00020000
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#define AC_TX_RESET 0x00040000
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#define AC_DMA 0x00080000
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#define AC_FIFO 0x00100000
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#define AC_NETWORK 0x00200000
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#define AC_HOST 0x00400000
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#define AC_AUTO_INIT 0x00800000
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#define AC_RESET_BUSY 0x04000000
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#define AC_LED_SPEED 0x08000000
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#define AC_LED_MODE_B1 0x20000000
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#define AC_RESET_ALL (AC_GB_RESET | AC_RX_RESET | AC_TX_RESET | AC_DMA | \
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AC_FIFO | AC_NETWORK | AC_HOST | AC_AUTO_INIT)
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/* Link Status */
|
||||
#define IC_LINK_UP 1
|
||||
#define IC_LINK_DOWN 0
|
||||
#define IC_LINK_UNKNOWN -1
|
||||
#define MC_DUPLEX_SEL 0x00000020
|
||||
#define MC_TX_FC_ENA 0x00000080
|
||||
#define MC_RX_FC_ENA 0x00000100
|
||||
#define MC_STAT_DISABLE 0x00400000
|
||||
#define MC_TX_ENABLE 0x01000000
|
||||
#define MC_TX_DISABLE 0x02000000
|
||||
#define MC_RX_ENABLE 0x08000000
|
||||
#define MC_RX_DISABLE 0x10000000
|
||||
#define MC_PAUSED 0x40000000
|
||||
|
||||
#define IC_RX_BUF_SIZE 1536
|
||||
#define IC_TX_BUF_SIZE 1536
|
||||
#define IC_RX_DESC_NUM 256
|
||||
#define IC_TX_DESC_NUM 256
|
||||
#define PC_DUPLEX_STS 0x10
|
||||
#define PC_LINK_SPEED 0xc0
|
||||
#define PC_LINK_SPEED10 0x40
|
||||
#define PC_LINK_SPEED100 0x80
|
||||
#define PC_LINK_SPEED1000 0xc0
|
||||
|
||||
/* #define IP1000_DEBUG */
|
||||
#define EC_READ 0x0200
|
||||
#define EC_BUSY 0x8000
|
||||
|
||||
/* Physical parameters */
|
||||
static const u16_t DefaultPhyParam[] = {
|
||||
(0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
|
||||
0x0000, 30, 0x005e, 9, 0x0700,
|
||||
(0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
|
||||
0x0000, 30, 0x005e, 9, 0x0700, 0x0000
|
||||
static u16_t PhyParam[] = {
|
||||
(0x4000|(07*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31, 0x0000,
|
||||
30, 0x005e, 9, 0x0700,
|
||||
(0x4100|(07*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31, 0x0000,
|
||||
30, 0x005e, 9, 0x0700,
|
||||
(0x4200|(07*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31, 0x0000,
|
||||
30, 0x005e, 9, 0x0700,
|
||||
(0x4300|(07*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31, 0x0000,
|
||||
30, 0x005e, 9, 0x0700, 0x0000
|
||||
};
|
||||
|
||||
/* Data Descriptor */
|
||||
/* ======= Data Descriptor ======= */
|
||||
typedef struct ic_desc {
|
||||
u64_t next_desc; /* Next descriptor */
|
||||
u64_t status; /* Status information */
|
||||
u64_t frag_info; /* Length and DMA buffer address */
|
||||
u64_t next;;
|
||||
u64_t status;;
|
||||
u64_t frag_info;;
|
||||
} ic_desc;
|
||||
|
||||
/* Driver Data Structure */
|
||||
typedef struct ic_driver {
|
||||
u16_t ic_base_addr; /* Base address */
|
||||
int ic_revision; /* Revision ID */
|
||||
int ic_irq; /* IRQ number */
|
||||
int ic_mode;
|
||||
int ic_link; /* Whether link-up */
|
||||
int ic_recv_flag; /* Receive flag */
|
||||
int ic_send_flag; /* Send flag */
|
||||
int ic_tx_alive;
|
||||
int ic_tx_busy;
|
||||
|
||||
/* LED mode read from EEPROM */
|
||||
u16_t ic_led_mode;
|
||||
|
||||
/* Station address read from EEPROM */
|
||||
u16_t sta_addr[3];
|
||||
u32_t base_addr; /* Base address */
|
||||
int revision; /* Revision ID */
|
||||
int irq; /* IRQ number */
|
||||
int mode;
|
||||
int link; /* Whether link-up */
|
||||
int recv_flag; /* Receive flag */
|
||||
int send_flag; /* Send flag */
|
||||
int tx_busy;
|
||||
|
||||
/* Buffer */
|
||||
size_t ic_buf_size;
|
||||
char *ic_buf;
|
||||
size_t buf_size;
|
||||
char *buf;
|
||||
|
||||
/* Rx data */
|
||||
int ic_rx_head;
|
||||
int rx_head;
|
||||
struct {
|
||||
phys_bytes buf_dma;
|
||||
char *buf;
|
||||
} ic_rx[IC_RX_DESC_NUM];
|
||||
ic_desc *ic_rx_desc; /* Rx descriptor buffer */
|
||||
phys_bytes ic_rx_desc_dma; /* Rx descriptor DMA buffer */
|
||||
} rx[RX_DESC_NUM];
|
||||
ic_desc *rx_desc; /* Rx descriptor buffer */
|
||||
phys_bytes rx_desc_dma; /* Rx descriptor DMA buffer */
|
||||
|
||||
/* Tx data */
|
||||
int ic_tx_head;
|
||||
int ic_tx_tail;
|
||||
int tx_head;
|
||||
int tx_tail;
|
||||
struct {
|
||||
int busy;
|
||||
phys_bytes buf_dma;
|
||||
char *buf;
|
||||
} ic_tx[IC_TX_DESC_NUM];
|
||||
ic_desc *ic_tx_desc; /* Tx descriptor buffer */
|
||||
phys_bytes ic_tx_desc_dma; /* Tx descriptor DMA buffer */
|
||||
int ic_tx_busy_num; /* Number of busy Tx descriptors */
|
||||
} tx[TX_DESC_NUM];
|
||||
ic_desc *tx_desc; /* Tx descriptor buffer */
|
||||
phys_bytes tx_desc_dma; /* Tx descriptor DMA buffer */
|
||||
int tx_busy_num; /* Number of busy Tx descriptors */
|
||||
|
||||
int ic_hook; /* IRQ hook id at kernel */
|
||||
eth_stat_t ic_stat;
|
||||
int hook; /* IRQ hook id at kernel */
|
||||
eth_stat_t stat;
|
||||
|
||||
char ic_name[20];
|
||||
char name[20];
|
||||
} ic_driver;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# Makefile for the VIA Technology 6105/6106S Ethernet driver (vt6105)
|
||||
PROG= vt6105
|
||||
PROG= vt6105
|
||||
SRCS= vt6105.c
|
||||
|
||||
FILES=${PROG}.conf
|
||||
|
|
|
|||
|
|
@ -1,15 +1,16 @@
|
|||
The vt6105 driver is for VIA Technology 6105/6106S Ethernet card.
|
||||
|
||||
This driver is referred to Minix(3.4.0) rtl8169 driver,
|
||||
This driver is referred to Minix(3.4.0) rtl8169 driver,
|
||||
Linux(4.2.1) via-rhine driver and VT6105 Rhine III Specification(Rev 1.2).
|
||||
|
||||
The supported PCI number is 1106:3106:1186:1403.
|
||||
Maybe other PCI numbers for VIA Rhine III can be supported.
|
||||
|
||||
Revision 1.0 2016/10/18
|
||||
Authored by Jia-Ju Bai <baijiaju1990@163.com>
|
||||
|
||||
Something can be improved:
|
||||
Revision 1.1 2016/11/12
|
||||
Modification: Remove and rewrite Linux-derived code
|
||||
Authored by Jia-Ju Bai <baijiaju1990@163.com>
|
||||
|
||||
Something can be improved:
|
||||
1. MII, WOL functions are not adequately defined and used.
|
||||
2. Link status report does not work well.
|
||||
3. Ethernet address can not be modified at present.
|
||||
|
|
|
|||
84
minix/drivers/net/vt6105/io.h
Normal file
84
minix/drivers/net/vt6105/io.h
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
#ifndef _IO_H
|
||||
#define _IO_H
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <minix/syslib.h>
|
||||
#include "vt6105.h"
|
||||
|
||||
/* I/O function */
|
||||
static u8_t my_inb(u32_t port) {
|
||||
u32_t value;
|
||||
int r;
|
||||
#ifdef DMA_REG_MODE
|
||||
value = *(u8_t *)(port);
|
||||
#else
|
||||
if ((r = sys_inb(port, &value)) != OK)
|
||||
printf("vt6105: sys_inb failed: %d\n", r);
|
||||
#endif
|
||||
return (u8_t)value;
|
||||
}
|
||||
#define vt_in8(port, offset) (my_inb((port) + (offset)))
|
||||
|
||||
static u16_t my_inw(u32_t port) {
|
||||
u32_t value;
|
||||
int r;
|
||||
#ifdef DMA_REG_MODE
|
||||
value = *(u16_t *)(port);
|
||||
#else
|
||||
if ((r = sys_inw(port, &value)) != OK)
|
||||
printf("vt6105: sys_inw failed: %d\n", r);
|
||||
#endif
|
||||
return (u16_t)value;
|
||||
}
|
||||
#define vt_in16(port, offset) (my_inw((port) + (offset)))
|
||||
|
||||
static u32_t my_inl(u32_t port) {
|
||||
u32_t value;
|
||||
int r;
|
||||
#ifdef DMA_REG_MODE
|
||||
value = *(u32_t *)(port);
|
||||
#else
|
||||
if ((r = sys_inl(port, &value)) != OK)
|
||||
printf("vt6105: sys_inl failed: %d\n", r);
|
||||
#endif
|
||||
return value;
|
||||
}
|
||||
#define vt_in32(port, offset) (my_inl((port) + (offset)))
|
||||
|
||||
static void my_outb(u32_t port, u8_t value) {
|
||||
int r;
|
||||
#ifdef DMA_REG_MODE
|
||||
*(u8_t *)(port) = value;
|
||||
#else
|
||||
if ((r = sys_outb(port, value)) != OK)
|
||||
printf("vt6105: sys_outb failed: %d\n", r);
|
||||
#endif
|
||||
}
|
||||
#define vt_out8(port, offset, value) \
|
||||
(my_outb(((port) + (offset)), (value)))
|
||||
|
||||
static void my_outw(u32_t port, u16_t value) {
|
||||
int r;
|
||||
#ifdef DMA_REG_MODE
|
||||
*(u16_t *)(port) = value;
|
||||
#else
|
||||
if ((r = sys_outw(port, value)) != OK)
|
||||
printf("vt6105: sys_outw failed: %d\n", r);
|
||||
#endif
|
||||
}
|
||||
#define vt_out16(port, offset, value) \
|
||||
(my_outw(((port) + (offset)), (value)))
|
||||
|
||||
static void my_outl(u16_t port, u32_t value) {
|
||||
int r;
|
||||
#ifdef DMA_REG_MODE
|
||||
*(u32_t *)(port) = value;
|
||||
#else
|
||||
if ((r = sys_outl(port, value)) != OK)
|
||||
printf("vt6105: sys_outl failed: %d\n", r);
|
||||
#endif
|
||||
}
|
||||
#define vt_out32(port, offset, value) \
|
||||
(my_outl(((port) + (offset)), (value)))
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,16 +1,17 @@
|
|||
service vt6105
|
||||
{
|
||||
type net;
|
||||
descr "VIA Technology 6105/6106S Ethernet Card";
|
||||
system
|
||||
UMAP # 14
|
||||
IRQCTL # 19
|
||||
DEVIO # 21
|
||||
;
|
||||
pci device 1106:3053;
|
||||
pci device 1106:3106;
|
||||
ipc
|
||||
SYSTEM pm rs log tty ds vm
|
||||
pci inet lwip amddev
|
||||
;
|
||||
type net;
|
||||
descr "VIA Technology 6105/6106S Ethernet Card";
|
||||
system
|
||||
UMAP # 14
|
||||
IRQCTL # 19
|
||||
DEVIO # 21
|
||||
;
|
||||
pci device 1106:3053;
|
||||
pci device 1106:3106;
|
||||
ipc
|
||||
SYSTEM pm rs log tty ds vm
|
||||
pci inet lwip amddev
|
||||
;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,194 +1,146 @@
|
|||
#ifndef _vt_H
|
||||
#define _vt_H
|
||||
|
||||
#include <minix/drivers.h>
|
||||
#include <minix/netdriver.h>
|
||||
#include <machine/pci.h>
|
||||
#include <minix/ds.h>
|
||||
#include <assert.h>
|
||||
|
||||
/* PCI Register */
|
||||
#define VT_PCI_VID 0x00 /* Vendor ID */
|
||||
#define VT_PCI_DID 0x02 /* Device ID */
|
||||
#define VT_PCI_CMD 0x04 /* Command */
|
||||
#define VT_PCI_STS 0x06 /* Status */
|
||||
#define VT_PCI_RID 0x08 /* Revision ID */
|
||||
#define VT_PCI_CC 0x09 /* Class Code */
|
||||
#define VT_PCI_CLS 0x0c /* Cache Line Size */
|
||||
#define VT_PCI_LT 0x0d /* Latency Timer */
|
||||
#define VT_PCI_HT 0x0e /* Header Type */
|
||||
/* ======= General Parameter ======= */
|
||||
/* Global configure */
|
||||
#define DESC_BASE64
|
||||
|
||||
/* Internal Register */
|
||||
#define VT_REG_ADDR 0x00 /* Ethernet Address */
|
||||
#define VT_REG_RCR 0x06 /* Receive Configure Request */
|
||||
#define VT_REG_TCR 0x07 /* Transmit Configure Request */
|
||||
#define VT_REG_CR 0x08 /* Control 0 */
|
||||
#define VT_REG_ISR 0x0c /* Interrupt Status */
|
||||
#define VT_REG_IMR 0x0e /* Interrupt Mask */
|
||||
#define VT_REG_MAR0 0x10 /* Multicast Address 0 */
|
||||
#define VT_REG_MAR1 0x14 /* Multicast Address 1 */
|
||||
#define VT_REG_RD_BASE 0x18 /* Receive Descriptor Base Address */
|
||||
#define VT_REG_TD_BASE 0x1c /* Transmit Descriptor Base Address */
|
||||
#define VT_REG_MII_CFG 0x6c /* MII Configuration */
|
||||
#define VT_REG_MII_STS 0x6d /* MII Status */
|
||||
#define VT_REG_BCR0 0x6e /* Bus Control 0 */
|
||||
#define VT_REG_BCR1 0x6f /* Bus Control 1 */
|
||||
#define VT_REG_MII_CR 0x70 /* MII Control */
|
||||
#define VT_REG_MII_ADDR 0x71 /* MII Interface Address*/
|
||||
#define VT_REG_MII_DATA 0x72 /* MII Data Port */
|
||||
#define VT_REG_EECSR 0x74 /* EEPROM Control/Status */
|
||||
#define VT_REG_CFG_A 0x78 /* Chip Configuration A */
|
||||
#define VT_REG_CFG_B 0x79 /* Chip Configuration B */
|
||||
#define VT_REG_CFG_C 0x7a /* Chip Configuration C */
|
||||
#define VT_REG_CFG_D 0x7b /* Chip Configuration D */
|
||||
#define VT_REG_MCR0 0x80 /* Miscellaneous Control 0 */
|
||||
#define VT_REG_MCR1 0x81 /* Miscellaneous Control 1 */
|
||||
#define VT_REG_STICK 0x83 /* Sticky Hardware Control */
|
||||
#define VT_REG_MISR 0x84 /* MII Interrupt Status */
|
||||
#define VT_REG_MIMR 0x86 /* MII Interrupt Mask */
|
||||
#define VT_REG_FCR0 0x98 /* Flow Control 0 */
|
||||
#define VT_REG_FCR1 0x99 /* Flow Control 1 */
|
||||
#define VT_REG_WOL_SET 0xA4 /* Wake On LAN Set */
|
||||
#define VT_REG_WOL_CLR 0xA0 /* Wake On LAN Clear */
|
||||
#define VT_REG_PCS_CLR 0xA5 /* Power Configuration Set */
|
||||
#define VT_REG_PCS_SET 0xA1 /* Power Configuration Clear */
|
||||
#define VT_REG_WOLC_SET 0xA7 /* WOL Configuration Set */
|
||||
#define VT_REG_WOLC_CLR 0xA3 /* WOL Configuration Clear */
|
||||
#define VT_REG_WOLS_SET 0xA8 /* WOL Status Clear */
|
||||
#define VT_REG_WOLS_CLR 0xAC /* WOL Status Set */
|
||||
/* Rx/Tx buffer parameter */
|
||||
#define RX_BUF_SIZE 1536
|
||||
#define TX_BUF_SIZE 1536
|
||||
#define RX_DESC_NUM 64
|
||||
#define TX_DESC_NUM 64
|
||||
|
||||
/* Interrupt Status/Mask Register */
|
||||
#define VT_INTR_RX_DONE 0x0001
|
||||
#define VT_INTR_TX_DONE 0x0002
|
||||
#define VT_INTR_RX_ERR 0x0004
|
||||
#define VT_INTR_TX_ERR 0x0008
|
||||
#define VT_INTR_RX_EMPTY 0x0020
|
||||
#define VT_INTR_PCI_ERR 0x0040
|
||||
#define VT_INTR_STS_MAX 0x0080
|
||||
#define VT_INTR_RX_EARLY 0x0100
|
||||
#define VT_INTR_TX_UNDER_RUN 0x0210
|
||||
#define VT_INTR_RX_OVERFLOW 0x0400
|
||||
#define VT_INTR_RX_DROPPED 0x0800
|
||||
#define VT_INTR_RX_NOBUF 0x1000
|
||||
#define VT_INTR_TX_ABORT 0x2000
|
||||
#define VT_INTR_PORT_CHANGE 0x4000
|
||||
#define VT_INTR_RX_WAKE_UP 0x8000
|
||||
/* Key internal register */
|
||||
#define REG_RCR 0x06
|
||||
#define REG_ISR 0x0c
|
||||
#define REG_IMR 0x0e
|
||||
#define REG_RX_DESC_BASEL 0x18
|
||||
#define REG_TX_DESC_BASEL 0x1c
|
||||
|
||||
/* Control Register Command */
|
||||
#define VT_CMD_START 0x0002
|
||||
#define VT_CMD_STOP 0x0004
|
||||
#define VT_CMD_RX_ON 0x0008
|
||||
#define VT_CMD_TX_ON 0x0010
|
||||
#define VT_CMD_TX_DEMAND 0x0020
|
||||
#define VT_CMD_RX_DEMAND 0x0040
|
||||
#define VT_CMD_EARLY_RX 0x0100
|
||||
#define VT_CMD_EARLY_TX 0x0200
|
||||
#define VT_CMD_FDUPLEX 0x0400
|
||||
#define VT_CMD_NO_POLL 0x0800
|
||||
#define VT_CMD_RESET 0x8000
|
||||
#ifdef DESC_BASE_DMA64
|
||||
#define REG_RX_DESC_BASEU 0
|
||||
#define REG_TX_DESC_BASEU 0
|
||||
#endif
|
||||
|
||||
/* Receive Configure Mode */
|
||||
#define VT_RCR_AP 0x10
|
||||
#define VT_RCR_AB 0x08
|
||||
#define VT_RCR_AM 0x04
|
||||
#define VT_RCR_AR 0x02
|
||||
#define VT_RCR_AE 0x01
|
||||
/* Key internal register width */
|
||||
#define WIDTH_REG_RCR 8
|
||||
#define WIDTH_REG_ISR 16
|
||||
#define WIDTH_REG_IMR 16
|
||||
|
||||
/* General Descriptor Flag */
|
||||
#define VT_DESC_OWN 0x80000000 /* Ownership */
|
||||
#define VT_DESC_FIRST 0x00000200 /* First Descriptor */
|
||||
#define VT_DESC_LAST 0x00000100 /* Last Descriptor */
|
||||
/* Interrupt statu and command */
|
||||
#define INTR_ISR_ERR 0x3ffc
|
||||
#define INTR_ISR_LINK_EVENT 0x4000
|
||||
#define INTR_ISR_RX_DONE 0x0001
|
||||
#define INTR_ISR_TX_DONE 0x0002
|
||||
#define INTR_ISR_CLEAR 0xbfbf
|
||||
#define INTR_IMR_ENABLE 0xfeff
|
||||
#define INTR_IMR_DISABLE 0x0000
|
||||
|
||||
/* Rx Descriptor Flag */
|
||||
#define VT_DESC_RX_LENMASK 0x7fff0000 /* Receive Frame Length Mask */
|
||||
#define VT_DESC_RX_OK 0x00008000 /* Receive OK */
|
||||
#define VT_DESC_RX_MAR 0x00002000 /* Multicast Address Received */
|
||||
#define VT_DESC_RX_BAR 0x00001000 /* Broadcast Address Received */
|
||||
#define VT_DESC_RX_PHY 0x00000800 /* Physical Address Received */
|
||||
#define VT_DESC_RX_LINK_ERR 0x00000080 /* Descriptor Link Structure Error */
|
||||
#define VT_DESC_RX_RUNT 0x00000020 /* Runt Packet */
|
||||
#define VT_DESC_RX_LONG 0x00000010 /* Long Packet */
|
||||
#define VT_DESC_RX_FOV 0x00000008 /* FIFO Overflow */
|
||||
#define VT_DESC_RX_FAE 0x00000004 /* Frame Align Error */
|
||||
#define VT_DESC_RX_CRCE 0x00000002 /* CRC Error */
|
||||
#define VT_DESC_RX_ERR 0x00000001 /* Receive Error */
|
||||
#define VT_DESC_RX_ALL_ERR (VT_DESC_RX_LINK_ERR | VT_DESC_RX_RUNT | \
|
||||
VT_DESC_RX_LONG | VT_DESC_RX_FOV | \
|
||||
VT_DESC_RX_FAE | VT_DESC_RX_CRCE | VT_DESC_RX_ERR)
|
||||
#define VT_DESC_RX_PACK (VT_DESC_FIRST | VT_DESC_LAST)
|
||||
/* Descriptor status */
|
||||
#define DESC_STATUS_RX_RECV_ERR 0x000000bf
|
||||
#define DESC_STATUS_RX_RECV_CLEAR 0x80000000
|
||||
#define DESC_STATUS_TX_SEND_ERR 0x00008f10
|
||||
#define DESC_STATUS_TX_SEND_CLEAR 0x00000000
|
||||
|
||||
/* Tx Descriptor Flag */
|
||||
#define VT_DESC_TX_ERR 0x00008000 /* Transmit Error */
|
||||
#define VT_DESC_TX_UDF 0x00000800 /* FIFO Underflow */
|
||||
#define VT_DESC_TX_CRS 0x00000400 /* Carrier Sense Lost Detect */
|
||||
#define VT_DESC_TX_OWC 0x00000200 /* Out of Window Collision */
|
||||
#define VT_DESC_TX_ABT 0x00000100 /* Excessive Collision Abort */
|
||||
#define VT_DESC_TX_CDH 0x00000010 /* Collision Detect */
|
||||
|
||||
/* WOL status */
|
||||
#define VT_WOL_UCAST 0x10
|
||||
#define VT_WOL_MAGIC 0x20
|
||||
#define VT_WOL_MCAST 0x30
|
||||
#define VT_WOL_LINK_UP 0x40
|
||||
#define VT_WOL_LINK_DOWN 0x80
|
||||
/* Rx mode */
|
||||
#define RCR_UNICAST 0x10
|
||||
#define RCR_MULTICAST 0x04
|
||||
#define RCR_BROADCAST 0x08
|
||||
|
||||
/* Link status */
|
||||
#define VT_LINK_UP 1
|
||||
#define VT_LINK_DOWN 0
|
||||
#define VT_LINK_UNKNOWN -1
|
||||
#define LINK_UP 1
|
||||
#define LINK_DOWN 0
|
||||
#define LINK_UNKNOWN -1
|
||||
|
||||
#define VT_RX_BUF_SIZE 1536
|
||||
#define VT_TX_BUF_SIZE 1536
|
||||
#define VT_RX_DESC_NUM 64
|
||||
#define VT_TX_DESC_NUM 64
|
||||
/* Basic Rx/Tx parameters */
|
||||
#define RX_BUF_SIZE 1536
|
||||
#define TX_BUF_SIZE 1536
|
||||
#define RX_DESC_NUM 64
|
||||
#define TX_DESC_NUM 64
|
||||
|
||||
/* #define VT6105_DEBUG */
|
||||
/* ======= Self-defined Parameter ======= */
|
||||
#define DESC_OWN 0x80000000
|
||||
#define DESC_FIRST 0x00000200
|
||||
#define DESC_LAST 0x00000100
|
||||
|
||||
/* Data Descriptor */
|
||||
#define DESC_RX_LENMASK 0x7fff0000
|
||||
#define DESC_RX_OK 0x00008000
|
||||
#define DESC_RX_NORMAL (DESC_FIRST | DESC_LAST)
|
||||
|
||||
#define REG_ADDR 0x00
|
||||
#define REG_TCR 0x07
|
||||
#define REG_CR 0x08
|
||||
#define REG_BCR0 0x6e
|
||||
#define REG_MCR1 0x81
|
||||
#define REG_STICK 0x83
|
||||
#define REG_MII_CFG 0x6c
|
||||
#define REG_MII_CR 0x70
|
||||
#define REG_MII_ADDR 0x71
|
||||
#define REG_MII_DATA 0x72
|
||||
#define REG_WOL_SET 0xa4
|
||||
#define REG_WOLC_SET 0xa7
|
||||
|
||||
#define CMD_START 0x0002
|
||||
#define CMD_STOP 0x0004
|
||||
#define CMD_RX_ON 0x0008
|
||||
#define CMD_TX_ON 0x0010
|
||||
#define CMD_TX_DEMAND 0x0020
|
||||
#define CMD_RX_DEMAND 0x0040
|
||||
#define CMD_FDUPLEX 0x0400
|
||||
#define CMD_NO_POLL 0x0800
|
||||
#define CMD_RESET 0x8000
|
||||
|
||||
/* ======= Data Descriptor ======= */
|
||||
typedef struct vt_desc {
|
||||
u32_t status; /* command/status */
|
||||
u32_t length; /* Buffer/Frame length */
|
||||
u32_t addr; /* DMA buffer address */
|
||||
u32_t next_desc; /* Next descriptor */
|
||||
u32_t status;
|
||||
u32_t length;
|
||||
u32_t addr;
|
||||
u32_t next;
|
||||
} vt_desc;
|
||||
|
||||
/* Driver Data Structure */
|
||||
typedef struct vt_driver {
|
||||
u16_t vt_base_addr; /* Base address */
|
||||
int vt_revision; /* Revision ID */
|
||||
int vt_irq; /* IRQ number */
|
||||
int vt_mode;
|
||||
int vt_link; /* Whether link-up */
|
||||
int vt_recv_flag; /* Receive flag */
|
||||
int vt_send_flag; /* Send flag */
|
||||
int vt_report_link;
|
||||
int vt_tx_alive;
|
||||
int vt_tx_busy;
|
||||
u32_t base_addr; /* Base address */
|
||||
int revision; /* Revision ID */
|
||||
int irq; /* IRQ number */
|
||||
int mode;
|
||||
int link; /* Whether link-up */
|
||||
int recv_flag; /* Receive flag */
|
||||
int send_flag; /* Send flag */
|
||||
int tx_busy;
|
||||
|
||||
/* Buffer */
|
||||
size_t vt_buf_size;
|
||||
char *vt_buf;
|
||||
size_t buf_size;
|
||||
char *buf;
|
||||
|
||||
/* Rx data */
|
||||
int vt_rx_head;
|
||||
int rx_head;
|
||||
struct {
|
||||
phys_bytes buf_dma;
|
||||
char *buf;
|
||||
} vt_rx[VT_RX_DESC_NUM];
|
||||
vt_desc *vt_rx_desc; /* Rx descriptor buffer */
|
||||
phys_bytes vt_rx_desc_dma; /* Rx descriptor DMA buffer */
|
||||
} rx[RX_DESC_NUM];
|
||||
vt_desc *rx_desc; /* Rx descriptor buffer */
|
||||
phys_bytes rx_desc_dma; /* Rx descriptor DMA buffer */
|
||||
|
||||
/* Tx data */
|
||||
int vt_tx_head;
|
||||
int vt_tx_tail;
|
||||
int tx_head;
|
||||
int tx_tail;
|
||||
struct {
|
||||
int busy;
|
||||
phys_bytes buf_dma;
|
||||
char *buf;
|
||||
} vt_tx[VT_TX_DESC_NUM];
|
||||
vt_desc *vt_tx_desc; /* Tx descriptor buffer */
|
||||
phys_bytes vt_tx_desc_dma; /* Tx descriptor DMA buffer */
|
||||
int vt_tx_busy_num; /* Number of busy Tx descriptors */
|
||||
} tx[TX_DESC_NUM];
|
||||
vt_desc *tx_desc; /* Tx descriptor buffer */
|
||||
phys_bytes tx_desc_dma; /* Tx descriptor DMA buffer */
|
||||
int tx_busy_num; /* Number of busy Tx descriptors */
|
||||
|
||||
int vt_hook; /* IRQ hook id at kernel */
|
||||
eth_stat_t vt_stat;
|
||||
int hook; /* IRQ hook id at kernel */
|
||||
eth_stat_t stat;
|
||||
|
||||
char vt_name[20];
|
||||
char name[20];
|
||||
} vt_driver;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user