kernel:WIP pending changes dynamic configuration.
Change-Id: I0f0ef014e5f341ad5df8c048863c8e5032b80950
This commit is contained in:
Kees Jongenburger
parent
7194772eae
commit
12987709f1
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@ -5,15 +5,15 @@
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* The base must be page aligned, so we round down and the kernel adds the
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* offset. The size must be a multiple of ARM_PAGE_SIZE, so we round up to 4KB.
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*/
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#ifdef AM335X
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#define PADCONF_REGISTERS_BASE 0x44E10000
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#define PADCONF_REGISTERS_OFFSET 0x0000
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#define PADCONF_REGISTERS_SIZE 0x1000 /* OFFSET + highest reg, rounded up */
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#elif DM37XX
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#define PADCONF_REGISTERS_BASE 0x48002000
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#define PADCONF_REGISTERS_OFFSET 0x0030
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#define PADCONF_REGISTERS_SIZE 0x1000 /* OFFSET + highest reg, rounded up */
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#endif
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//#ifdef AM335X
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#define PADCONF_AM335X_REGISTERS_BASE 0x44E10000
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#define PADCONF_AM335X_REGISTERS_OFFSET 0x0000
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#define PADCONF_AM335X_REGISTERS_SIZE 0x1000 /* OFFSET + highest reg, rounded up */
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//#elif DM37XX
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#define PADCONF_DM37XX_REGISTERS_BASE 0x48002000
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#define PADCONF_DM37XX_REGISTERS_OFFSET 0x0030
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#define PADCONF_DM37XX_REGISTERS_SIZE 0x1000 /* OFFSET + highest reg, rounded up */
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//#endif
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#define PADCONF_MUXMODE(X) (X & 0x7) /* mode 1 til 7 [2:0] */
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#define PADCONF_PULL_MODE(X) ((X & 0x3) << 3) /* 2 bits[4:3] */
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@ -7,6 +7,7 @@
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#include "kernel/proc.h"
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#include "kernel/interrupt.h"
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#include <minix/u64.h>
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#include <minix/board.h>
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#include "kernel/glo.h"
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#include "kernel/profile.h"
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@ -28,12 +29,14 @@ int init_local_timer(unsigned freq)
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{
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omap3_timer_init(freq);
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omap3_frclock_init();
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#ifdef DM37XX
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tsc_per_ms[0] = 16250;
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#endif
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#ifdef AM335X
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tsc_per_ms[0] = 15000;
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#endif
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if (BOARD_IS_BBXM(machine.board_id)){
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tsc_per_ms[0] = 16250;
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} else if (BOARD_IS_BB(machine.board_id)){
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tsc_per_ms[0] = 15000;
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} else {
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panic("Can not do the clock setup. machine (0x%08x) is unknown\n",machine.board_id);
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};
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return 0;
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}
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@ -4,9 +4,9 @@
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#if USE_PADCONF
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/* get arch specific arch_padconf_set() */
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#if defined(AM335X) || defined(DM37XX)
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//#if defined(AM335X) || defined(DM37XX)
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#include "omap_padconf.h"
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#endif
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//#endif
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/*===========================================================================*
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* do_padconf *
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@ -410,6 +410,17 @@ static inline void write_vbar(u32_t vbar)
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isb();
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}
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#define MIDR_IMPLEMENTER_SHIFT (24)
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#define MIDR_IMPLEMENTER_MASK (0xFF << MIDR_IMPLEMENTER_SHIFT)
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#define MIDR_MAJOR_REV_SHIFT (20)
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#define MIDR_MAJOR_REV_MASK (0xF << MIDR_MAJOR_REV_SHIFT)
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#define MIDR_ARCH_CODE_SHIFT (16)
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#define MIDR_ARCH_CODE_MASK (0xF << MIDR_ARCH_CODE_SHIFT)
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#define MIDR_PART_NUMBER_SHIFT (4)
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#define MIDR_PART_NUMBER_MASK (0xFFF << MIDR_PART_NUMBER_SHIFT)
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#define MIDR_MINOR_REV_SHIFT (0)
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#define MIDR_MINOR_REV_MASK (0xF << MIDR_MINOR_REV_SHIFT)
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/* Read the Main ID Register */
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static inline u32_t read_midr()
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{
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@ -6,6 +6,7 @@
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#include <machine/vm.h>
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#include <minix/type.h>
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#include <minix/board.h>
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#include <minix/syslib.h>
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#include <minix/cpufeature.h>
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#include <string.h>
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@ -737,12 +738,13 @@ int arch_phys_map(const int index,
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}
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else if (index == frclock_index) {
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#ifdef DM37XX
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*addr = OMAP3_GPTIMER10_BASE;
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#endif
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#ifdef AM335X
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*addr = AM335X_DMTIMER7_BASE;
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#endif
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if (BOARD_IS_BBXM(machine.board_id)){
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*addr = OMAP3_GPTIMER10_BASE;
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} else if (BOARD_IS_BB(machine.board_id)){
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*addr = AM335X_DMTIMER7_BASE;
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} else {
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panic("Can not do the clock setup. machine (0x%08x) is unknown\n",machine.board_id);
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};
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*len = ARM_PAGE_SIZE;
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*flags = VMMF_UNCACHED | VMMF_USER;
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return OK;
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@ -792,15 +794,15 @@ int arch_phys_map_reply(const int index, const vir_bytes addr)
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return OK;
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}
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else if (index == frclock_index) {
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#if defined(DM37XX)
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minix_kerninfo.minix_frclock_tcrr = addr + OMAP3_TIMER_TCRR;
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minix_kerninfo.minix_arm_frclock_hz = 1625000;
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#elif defined(AM335X)
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minix_kerninfo.minix_frclock_tcrr = addr + AM335X_TIMER_TCRR;
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minix_kerninfo.minix_arm_frclock_hz = 1500000;
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#else
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#error ARM: plese define either AM335X or DM37XX.
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#endif
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if (BOARD_IS_BBXM(machine.board_id)){
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minix_kerninfo.minix_frclock_tcrr = addr + OMAP3_TIMER_TCRR;
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minix_kerninfo.minix_arm_frclock_hz = 1625000;
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} else if (BOARD_IS_BB(machine.board_id)){
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minix_kerninfo.minix_frclock_tcrr = addr + AM335X_TIMER_TCRR;
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minix_kerninfo.minix_arm_frclock_hz = 1500000;
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} else {
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panic("memory setup errot machine (0x%08x) is unhandled\n",machine.board_id);
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};
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return OK;
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}
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@ -1,6 +1,7 @@
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#include <sys/types.h>
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#include <machine/cpu.h>
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#include <minix/type.h>
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#include <minix/board.h>
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#include <io.h>
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#include "kernel/kernel.h"
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@ -21,12 +22,13 @@ static kern_phys_map intr_phys_map;
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int intr_init(const int auto_eoi)
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{
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#ifdef DM37XX
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omap_intr.base = OMAP3_DM37XX_INTR_BASE;
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#endif
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#ifdef AM335X
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omap_intr.base = OMAP3_AM335X_INTR_BASE;
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#endif
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if (BOARD_IS_BBXM(machine.board_id)){
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omap_intr.base = OMAP3_DM37XX_INTR_BASE;
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} else if (BOARD_IS_BB(machine.board_id)){
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omap_intr.base = OMAP3_AM335X_INTR_BASE;
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} else {
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panic("Can not do the interrupt setup. machine (0x%08x) is unknown\n",machine.board_id);
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};
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omap_intr.size = 0x1000 ; /* 4K */
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kern_phys_map_ptr(omap_intr.base,omap_intr.size,
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@ -1,16 +1,16 @@
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#ifndef _OMAP_INTR_H
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#define _OMAP_INTR_H
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#ifdef DM37XX
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//#ifdef DM37XX
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/* Interrupt controller memory map */
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#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
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#endif /* DM37XX */
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//#endif /* DM37XX */
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#ifdef AM335X
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//#ifdef AM335X
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/* Interrupt controller memory map */
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#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
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#endif /* AM335X */
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//#endif /* AM335X */
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/* Interrupt controller registers */
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#define OMAP3_INTCPS_REVISION 0x000 /* IP revision code */
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@ -59,7 +59,7 @@
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#ifdef DM37XX
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//#ifdef DM37XX
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#define OMAP3_DM337X_NR_IRQ_VECTORS 96
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@ -135,9 +135,9 @@
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#define OMAP3_HSUSB_DMA_IRQ 93 /* High-speed USB OTG DMA */
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#define OMAP3_MMC3_IRQ 94 /* MMC/SD module 3 */
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#endif
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//#endif
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#ifdef AM335X
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//#ifdef AM335X
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#define AM335X_INT_EMUINT 0 /* Emulation interrupt (EMUICINTR) */
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#define AM335X_INT_COMMTX 1 /* CortexA8 COMMTX */
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#define AM335X_INT_COMMRX 2 /* CortexA8 COMMRX */
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@ -239,7 +239,7 @@
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#define AM335X_INT_SPI1INT 125 /* McSPI1 SINTERRUPTN */
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#define OMAP3_AM335X_NR_IRQ_VECTORS 125
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#endif
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//#endif
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#ifndef __ASSEMBLY__
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@ -6,6 +6,7 @@
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#include <machine/cpu.h>
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#include <minix/mmio.h>
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#include <minix/padconf.h>
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#include <minix/board.h>
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#include <assert.h>
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#include <io.h>
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#include <stdlib.h>
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@ -18,25 +19,43 @@ struct omap_padconf
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vir_bytes base;
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vir_bytes offset;
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vir_bytes size;
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unsigned int board_filter_value;
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unsigned int board_filter_mask;
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};
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static struct omap_padconf omap_padconf = {
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.base = PADCONF_REGISTERS_BASE,
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.offset = PADCONF_REGISTERS_OFFSET,
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.size = PADCONF_REGISTERS_SIZE
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struct omap_padconf omap_padconfs[] = {
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{
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.base = PADCONF_DM37XX_REGISTERS_BASE,
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.offset = PADCONF_DM37XX_REGISTERS_OFFSET,
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.size = PADCONF_DM37XX_REGISTERS_SIZE,
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.board_filter_value = BOARD_FILTER_BBXM_VALUE,
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.board_filter_mask = BOARD_FILTER_BBXM_MASK,
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},
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{
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.base = PADCONF_AM335X_REGISTERS_BASE,
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.offset = PADCONF_AM335X_REGISTERS_OFFSET,
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.size = PADCONF_AM335X_REGISTERS_SIZE,
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.board_filter_value = BOARD_FILTER_BB_VALUE,
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.board_filter_mask = BOARD_FILTER_BB_MASK,
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},
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};
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/* initialized in init */
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static struct omap_padconf *omap_padconf;
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static kern_phys_map padconf_phys_map;
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int
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arch_padconf_set(u32_t padconf, u32_t mask, u32_t value)
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{
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/* check that the value will be inside the padconf memory range */
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if (padconf >= (PADCONF_REGISTERS_SIZE - PADCONF_REGISTERS_OFFSET)) {
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if (padconf >= (omap_padconf->size - omap_padconf->offset)) {
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return EINVAL; /* outside of valid range */
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}
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set32(padconf + omap_padconf.base + omap_padconf.offset, mask, value);
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set32(padconf + omap_padconf->base + omap_padconf->offset, mask, value);
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return OK;
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}
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@ -44,8 +63,19 @@ arch_padconf_set(u32_t padconf, u32_t mask, u32_t value)
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void
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arch_padconf_init(void)
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{
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kern_phys_map_ptr(omap_padconf.base, omap_padconf.size,
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&padconf_phys_map, (vir_bytes) &omap_padconf.base);
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int x;
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omap_padconf = NULL;
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/* find the correct padconf */
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for (x =0 ; x < sizeof(omap_padconfs)/sizeof(omap_padconfs[0]) ; x++){
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if ( (omap_padconfs[x].board_filter_mask & machine.board_id) == omap_padconfs[x].board_filter_value){
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omap_padconf = &omap_padconfs[x];
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break;
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}
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}
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assert(omap_padconf);
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kern_phys_map_ptr(omap_padconf->base, omap_padconf->size,
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&padconf_phys_map, (vir_bytes) &omap_padconf->base);
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return;
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}
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@ -2,6 +2,7 @@
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#include <sys/types.h>
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#include <machine/cpu.h>
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#include <minix/type.h>
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#include <minix/board.h>
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#include <io.h>
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#include "kernel/kernel.h"
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@ -11,21 +12,17 @@
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#include "arch_proto.h"
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#include "omap_reset.h"
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#ifdef AM335X
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#define CM_BASE 0x44E00000
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#define CM_SIZE 0x1000
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#define PRM_DEVICE_OFFSET 0xf00
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#define PRM_RSTCTRL_REG 0x00
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#define RST_GLOBAL_WARM_SW_BIT 0
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#elif DM37XX
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#define CM_BASE 0x48307000
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#define CM_SIZE 0x1000
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#define PRM_RSTCTRL_REG 0x250
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#define RST_DPLL3_BIT 2
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#else
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#define CM_BASE 0x00000000
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#define CM_SIZE 0x1000
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#endif
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#define AM335X_CM_BASE 0x44E00000
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#define AM335X_CM_SIZE 0x1000
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#define AM335X_PRM_DEVICE_OFFSET 0xf00
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#define AM335X_PRM_RSTCTRL_REG 0x00
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#define AM335X_RST_GLOBAL_WARM_SW_BIT 0
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#define DM37XX_CM_BASE 0x48307000
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#define DM37XX_CM_SIZE 0x1000
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#define DM37XX_PRM_RSTCTRL_REG 0x250
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#define DM37XX_RST_DPLL3_BIT 2
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struct omap_reset
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{
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@ -33,28 +30,32 @@ struct omap_reset
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vir_bytes size;
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};
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static struct omap_reset omap_reset = {
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.base = CM_BASE,
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.size = CM_SIZE
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};
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static struct omap_reset omap_reset;
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static kern_phys_map reset_phys_map;
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void
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omap3_reset_init(void)
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{
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#if defined(AM335X) || defined(DM37XX)
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if(BOARD_IS_BBXM(machine.board_id)){
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omap_reset.base = DM37XX_CM_BASE;
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omap_reset.size = DM37XX_CM_SIZE;
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} else if(BOARD_IS_BB(machine.board_id)){
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omap_reset.base = AM335X_CM_BASE;
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omap_reset.size = AM335X_CM_SIZE;
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}
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kern_phys_map_ptr(omap_reset.base, omap_reset.size, &reset_phys_map,
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(vir_bytes) &omap_reset.base);
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#endif /* AM335X || DM37XX */
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}
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void
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omap3_reset(void)
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{
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#ifdef AM335X
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mmio_set((omap_reset.base + PRM_DEVICE_OFFSET + PRM_RSTCTRL_REG), (1 << RST_GLOBAL_WARM_SW_BIT));
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#elif DM37XX
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mmio_set((omap_reset.base + PRM_RSTCTRL_REG), (1 << RST_DPLL3_BIT));
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#endif
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if(BOARD_IS_BBXM(machine.board_id)){
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mmio_set((omap_reset.base + DM37XX_PRM_RSTCTRL_REG), (1 << DM37XX_RST_DPLL3_BIT));
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} else if(BOARD_IS_BB(machine.board_id)){
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mmio_set((omap_reset.base + AM335X_PRM_DEVICE_OFFSET + AM335X_PRM_RSTCTRL_REG), (1 << AM335X_RST_GLOBAL_WARM_SW_BIT));
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}
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}
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@ -2,6 +2,7 @@
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#include "kernel/clock.h"
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#include <sys/types.h>
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#include <machine/cpu.h>
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#include <minix/board.h>
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#include <minix/mmio.h>
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#include <assert.h>
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#include <io.h>
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@ -157,37 +158,37 @@ void omap3_frclock_init(void)
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&fr_timer_phys_map, (vir_bytes) &fr_timer.base);
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/* enable the clock */
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#ifdef AM335X
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/* Disable the module and wait for the module to be disabled */
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set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK,CM_MODULEMODE_DISABLED);
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while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_DISABLE);
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if(BOARD_IS_BBXM(machine.board_id)){
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/* Stop timer */
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mmio_clear(fr_timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
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set32(CLKSEL_TIMER7_CLK,CLKSEL_TIMER7_CLK_SEL_MASK, CLKSEL_TIMER7_CLK_SEL_SEL2);
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while( (read32(CLKSEL_TIMER7_CLK) & CLKSEL_TIMER7_CLK_SEL_MASK) != CLKSEL_TIMER7_CLK_SEL_SEL2);
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/* Use functional clock source for GPTIMER10 */
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mmio_set(OMAP3_CM_CLKSEL_CORE, OMAP3_CLKSEL_GPT10);
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||||
/* enable the module and wait for the module to be ready */
|
||||
set32(CM_PER_TIMER7_CLKCTRL,CM_MODULEMODE_MASK,CM_MODULEMODE_ENABLE);
|
||||
while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_FUNC);
|
||||
#endif
|
||||
/* Scale timer down to 13/8 = 1.625 Mhz to roughly get microsecond ticks */
|
||||
/* The scale is computed as 2^(PTV+1). So if PTV == 2, we get 2^3 = 8.
|
||||
*/
|
||||
mmio_set(fr_timer.base + fr_timer.regs->TCLR, (2 << OMAP3_TCLR_PTV));
|
||||
} else if(BOARD_IS_BB(machine.board_id)){
|
||||
/* Disable the module and wait for the module to be disabled */
|
||||
set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK,CM_MODULEMODE_DISABLED);
|
||||
while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_DISABLE);
|
||||
|
||||
/* Stop timer */
|
||||
mmio_clear(fr_timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
|
||||
set32(CLKSEL_TIMER7_CLK,CLKSEL_TIMER7_CLK_SEL_MASK, CLKSEL_TIMER7_CLK_SEL_SEL2);
|
||||
while( (read32(CLKSEL_TIMER7_CLK) & CLKSEL_TIMER7_CLK_SEL_MASK) != CLKSEL_TIMER7_CLK_SEL_SEL2);
|
||||
|
||||
/* enable the module and wait for the module to be ready */
|
||||
set32(CM_PER_TIMER7_CLKCTRL,CM_MODULEMODE_MASK,CM_MODULEMODE_ENABLE);
|
||||
while( (mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_FUNC);
|
||||
|
||||
/* Stop timer */
|
||||
mmio_clear(fr_timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
|
||||
|
||||
/* 24Mhz / 16 = 1.5 Mhz */
|
||||
mmio_set(fr_timer.base + fr_timer.regs->TCLR, (3 << OMAP3_TCLR_PTV));
|
||||
}
|
||||
|
||||
#ifdef DM37XX
|
||||
/* Use functional clock source for GPTIMER10 */
|
||||
mmio_set(OMAP3_CM_CLKSEL_CORE, OMAP3_CLKSEL_GPT10);
|
||||
#endif
|
||||
|
||||
#ifdef DM37XX
|
||||
/* Scale timer down to 13/8 = 1.625 Mhz to roughly get microsecond ticks */
|
||||
/* The scale is computed as 2^(PTV+1). So if PTV == 2, we get 2^3 = 8.
|
||||
*/
|
||||
mmio_set(fr_timer.base + fr_timer.regs->TCLR, (2 << OMAP3_TCLR_PTV));
|
||||
#endif
|
||||
#ifdef AM335X
|
||||
/* 24Mhz / 16 = 1.5 Mhz */
|
||||
mmio_set(fr_timer.base + fr_timer.regs->TCLR, (3 << OMAP3_TCLR_PTV));
|
||||
#endif
|
||||
|
||||
/* Start and auto-reload at 0 */
|
||||
mmio_write(fr_timer.base + fr_timer.regs->TLDR, 0x0);
|
||||
|
|
@ -230,11 +231,15 @@ void omap3_timer_init(unsigned freq)
|
|||
/* enable the module and wait for the module to be ready */
|
||||
set32(CM_WKUP_TIMER1_CLKCTRL,CM_MODULEMODE_MASK,CM_MODULEMODE_ENABLE);
|
||||
while( (mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST) != CM_CLKCTRL_IDLEST_FUNC);
|
||||
|
||||
/* Stop timer */
|
||||
mmio_clear(timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
|
||||
#endif
|
||||
|
||||
#ifdef DM37XX
|
||||
/* Stop timer */
|
||||
mmio_clear(timer.base + fr_timer.regs->TCLR, OMAP3_TCLR_ST);
|
||||
|
||||
#ifdef DM37XX
|
||||
/* Use 32 KHz clock source for GPTIMER1 */
|
||||
mmio_clear(OMAP3_CM_CLKSEL_WKUP, OMAP3_CLKSEL_GPT1);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#ifndef _OMAP_TIMER_REGISTERS_H
|
||||
#define _OMAP_TIMER_REGISTERS_H
|
||||
|
||||
#ifdef DM37XX
|
||||
//#ifdef DM37XX
|
||||
|
||||
/* General-purpose timer register map */
|
||||
#define OMAP3_GPTIMER1_BASE 0x48318000 /* GPTIMER1 physical address */
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
#define OMAP3_GPTIMER10_BASE 0x48086000 /* GPTIMER10 physical address */
|
||||
#define OMAP3_GPTIMER11_BASE 0x48088000 /* GPTIMER11 physical address */
|
||||
|
||||
#endif /* DM37XX */
|
||||
//#endif /* DM37XX */
|
||||
|
||||
/* General-purpose timer registers */
|
||||
#define OMAP3_TIMER_TIDR 0x000 /* IP revision code */
|
||||
|
|
@ -40,7 +40,7 @@
|
|||
#define OMAP3_TIMER_TOCR 0x054 /* Masks tick interrupt */
|
||||
#define OMAP3_TIMER_TOWR 0x058 /* Number of masked overflow interrupts */
|
||||
|
||||
#ifdef AM335X
|
||||
//#ifdef AM335X
|
||||
#define AM335X_DMTIMER0_BASE 0x44E05000 /* DMTimer0 Registers */
|
||||
#define AM335X_DMTIMER1_1MS_BASE 0x44E31000 /* DMTimer1 1ms Registers (Accurate 1ms timer) */
|
||||
#define AM335X_DMTIMER2_BASE 0x48040000 /* DMTimer2 Registers */
|
||||
|
|
@ -68,7 +68,7 @@
|
|||
#define AM335X_TIMER_TSICR 0x054 /* Control posted mode and functional SW reset */
|
||||
#define AM335X_TIMER_TCAR2 0x058 /* Second captured value of counter register */
|
||||
|
||||
#endif
|
||||
//#endif
|
||||
|
||||
|
||||
/* Interrupt status register fields */
|
||||
|
|
@ -88,7 +88,7 @@
|
|||
#define OMAP3_TCLR_PTV 2
|
||||
#define OMAP3_TCLR_OVF_TRG (1 << 10) /* Overflow trigger */
|
||||
|
||||
#ifdef DM37XX
|
||||
//#ifdef DM37XX
|
||||
|
||||
#define OMAP3_CM_CLKSEL_GFX 0x48004b40
|
||||
#define OMAP3_CM_CLKEN_PLL 0x48004d00
|
||||
|
|
@ -98,9 +98,9 @@
|
|||
#define OMAP3_CM_CLKSEL_PER 0x48005040
|
||||
#define OMAP3_CM_CLKSEL_WKUP 0x48004c40 /* GPT1 source clock selection */
|
||||
|
||||
#endif /* DM37XX */
|
||||
//#endif /* DM37XX */
|
||||
|
||||
#ifdef AM335X
|
||||
//#ifdef AM335X
|
||||
|
||||
#define CM_MODULEMODE_MASK (0x3 << 0)
|
||||
#define CM_MODULEMODE_ENABLE (0x2 << 0)
|
||||
|
|
@ -146,7 +146,7 @@
|
|||
|
||||
|
||||
|
||||
#endif /* AM335X */
|
||||
//#endif /* AM335X */
|
||||
|
||||
#define OMAP3_CLKSEL_GPT1 (1 << 0) /* Selects GPTIMER 1 source
|
||||
* clock:
|
||||
|
|
|
|||
|
|
@ -277,6 +277,70 @@ void get_parameters(u32_t ebx, kinfo_t *cbi)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
#define OMAP3_ROM_ADDRESS 0x40000000
|
||||
#define OMAP3_ROM_SIZE 0x00020000
|
||||
|
||||
|
||||
struct omap_rom_sum {
|
||||
u32_t sum;
|
||||
u32_t board_id;
|
||||
};
|
||||
|
||||
static struct omap_rom_sum omap_rom_sum[] = {
|
||||
{ .sum = 0x2185, .board_id = BOARD_ID_BBW },
|
||||
};
|
||||
|
||||
void determine_omap_board_id(){
|
||||
/* for am335x read 0x44E10600 */
|
||||
//27-12 (See AM335x errata for specific information on each revision.)
|
||||
//11-1 (Device part number 0xB944)
|
||||
|
||||
|
||||
/*
|
||||
* 16-bit checksum, rotating right before each addition;
|
||||
* overflow is discarded.
|
||||
*/
|
||||
u_char *p;
|
||||
u32_t count = 0;
|
||||
u_int lcrc = 0;
|
||||
p = (char *) OMAP3_ROM_ADDRESS;
|
||||
|
||||
for (count =0 ; count < OMAP3_ROM_SIZE ; count++){
|
||||
if (lcrc & 1) { lcrc |= 0x10000; }
|
||||
lcrc = ((lcrc >> 1) + *p) & 0xffff;
|
||||
p++;
|
||||
}
|
||||
/* calculate a BSD compatible checksum of the rom code */
|
||||
printf("ROM sum 0x%04x\n",lcrc);
|
||||
}
|
||||
|
||||
void determine_board_id(){
|
||||
|
||||
u32_t midr = read_midr();
|
||||
u32_t impl = (midr & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT;
|
||||
u32_t major = (midr & MIDR_MAJOR_REV_MASK) >> MIDR_MAJOR_REV_SHIFT;
|
||||
u32_t arch_code = (midr & MIDR_ARCH_CODE_MASK) >> MIDR_ARCH_CODE_SHIFT;
|
||||
u32_t part_nr = (midr & MIDR_PART_NUMBER_MASK) >> MIDR_PART_NUMBER_SHIFT;
|
||||
u32_t minor = (midr & MIDR_MINOR_REV_MASK) >> MIDR_MINOR_REV_SHIFT;
|
||||
|
||||
|
||||
/* ARMv7 Must have 0x41 as implementer code */
|
||||
assert(impl == 0x41);
|
||||
|
||||
/* if arch code equals 0xf we need to read out the cpuid register */
|
||||
if (arch_code == 0xf){
|
||||
|
||||
}
|
||||
printf("ID 0x%08x\n",midr);
|
||||
printf("ID IMPL MASKED%08x\n",midr & MIDR_IMPLEMENTER_MASK);
|
||||
|
||||
printf(" IMPL= 0x%x\nmajor= 0x%x\nminor= 0x%x\n arch_code= 0x%0x\n part_nr= 0x%0x\n",impl,major,minor,arch_code,part_nr);
|
||||
determine_omap_board_id();
|
||||
}
|
||||
|
||||
kinfo_t *pre_init(u32_t magic, u32_t ebx)
|
||||
{
|
||||
/* Clear BSS */
|
||||
|
|
@ -287,6 +351,7 @@ kinfo_t *pre_init(u32_t magic, u32_t ebx)
|
|||
* Here we find out whether we should do serial output.
|
||||
*/
|
||||
get_parameters(ebx, &kinfo);
|
||||
determine_board_id();
|
||||
|
||||
/* Make and load a pagetable that will map the kernel
|
||||
* to where it should be; but first a 1:1 mapping so
|
||||
|
|
@ -314,3 +379,4 @@ void busy_delay_ms(int x) { }
|
|||
int raise(int n) { panic("raise(%d)\n", n); }
|
||||
int kern_phys_map_ptr( phys_bytes base_address, vir_bytes io_size,
|
||||
struct kern_phys_map * priv, vir_bytes ptr) {};
|
||||
struct machine machine;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user